US-12626666-B2 - Gate driver and display device including the same

US12626666B2US 12626666 B2US12626666 B2US 12626666B2US-12626666-B2

Abstract

A display device includes gate lines and pixels connected to the gate lines. The display device includes stages which provide gate signals to the gate lines, and first and second gate power lines which transfer a first voltage to the stages. A first stage among the stages includes a first node controller and a first output unit. The first node controller is connected to the second gate power line, and controls a voltage of a first control node. The first output unit is connected to the first gate power line, and outputs a first voltage of the first gate power line as a gate signal in response to a voltage of the first control node.

Inventors

Hai Jung In

Assignees

SAMSUNG DISPLAY CO., LTD.

Dates

Publication Date: 20260512
Application Date: 20240522
Priority Date: 20200605

Claims (13)

1 . A display device comprising: a plurality of pixels formed in a display area; a first gate driver formed in a first gate circuit area, the first gate driver being coupled to a first gate power line; a second gate driver formed in the first gate circuit area, the second gate driver being coupled to a second gate power line; and a first pad formed in a pad area, the first pad receiving a gate power voltage, wherein the first gate power line and the second gate power line are connected to each other in a first region between the first and second gate drivers and the first pad, and then connected to the first pad, and wherein the gate power voltage from the first pad is applied to the first gate driver through the first gate power line and the gate power voltage from the first pad is applied to the second gate driver through the second gate power line.
2 . The display device of claim 1 , wherein the first gate driver output emission gate signals to emission gate lines connected to the plurality of pixels, and the second gate driver output write gate signals to write gate lines connected to the plurality of pixels.
3 . The display device of claim 1 , wherein the second gate driver is located between the display area and the first gate driver.
4 . The display device of claim 1 , further comprising: a third gate driver formed in the first gate circuit area, the third gate driver being coupled to a third gate power line and a fourth gate power line; and a second pad formed in the pad area, wherein the third gate power line and the fourth gate power line are connected to each other in a second region between the third gate driver and the second pad, and then connected to the second pad.
5 . The display device of claim 4 , wherein the second gate driver is located between the display area and the first and third gate drivers, and the third gate driver is located between the second gate driver and the first gate driver.
6 . The display device of claim 4 , wherein the third gate driver is further coupled to a fifth gate power line, and the fifth gate power line is connected to the third and fourth gate power lines in the second region.
7 . The display device of claim 6 , wherein the fifth gate power line is connected to the second gate power line at an upper side of the first gate circuit area.
8 . The display device of claim 7 , wherein the fifth gate power line is further connected to the first gate power line at the upper side of the first gate circuit area.
9 . The display device of claim 1 , further comprising: a third gate driver including a plurality of stages, wherein the plurality of stages includes a first stage and a second stage adjacent to the first stage, wherein the first stage includes a ninth transistor electrically connected between a third gate power line and an output terminal of the first stage, wherein the second stage includes a ninth transistor electrically connected between a fourth gate power line and an output terminal of the second stage.
10 . The display device of claim 1 , further comprising: a fourth gate driver formed in a second gate circuit area, the fourth gate driver being coupled to the third gate power line and a fourth gate power line; and a third pad formed in the pad area, wherein the first gate circuit area is located at a first side of the display are, wherein the second gate circuit area is located at a second side of the display area that is opposite to the first side.
11 . The display device of claim 10 , wherein the third gate power line and the fourth gate power line are connected to the third pad in the pad area.
12 . The display device of claim 1 , further comprising: a fourth gate driver formed in a second gate circuit area, the fourth gate driver being coupled to a third gate power line, a fourth gate power line and a fifth gate line; and a third pad formed in the pad area, wherein the first gate circuit area is located at a first side of the display are, wherein the second gate circuit area is located at a second side of the display area that is opposite to the first side.
13 . The display device of claim 12 , wherein the third gate power line, the fourth gate power line and the fifth gate line are connected to the third pad in the pad area.

Description

The application is a continuation of U.S. patent application Ser. No. 18/106,321, filed on Feb. 6, 2023, which is a continuation of U.S. patent application Ser. No. 17/205,203, filed on Mar. 18, 2021, which claims priority to Korean patent application 10-2020-0068442, filed on Jun. 5, 2020, and all the benefits accruing therefrom under 35 U.S.C. § 119, the content of which in its entirety is herein incorporated by reference. BACKGROUND 1. Field The disclosure generally relates to a gate driver and a display device including the gate driver. 2. Description of the Related Art A display device typically includes a data driver, a gate driver, and pixels. The data driver may provide data signals to the pixels through data lines. The gate driver may generate a gate signal by using a gate power source and a clock signal, which are provided from an outside, and sequentially provide the gate signal to the pixels through gate lines. For example, the gate driver outputs the gate power source as the gate signal having a turn-on level in response to the clock signal. Each of the pixels may receive a corresponding data signal in response to the gate signal, and emit light, corresponding to the data signal. SUMMARY In a display device, when a gate signal is supplied to a gate line, a fluctuation may occur in the gate power source while a line capacitance of the gate line is charged. Since gate signals are sequentially output, a periodic fluctuation (or ripple) may occur in the gate power source which becomes the basis of the gate signal, and a fluctuation may occur in gate signals generated based on the gate power source. A pixel which receives a data signal at a time at which a fluctuation occurs in a gate signal may emits light with a luminance different from that of the pixel which receives a data signal at a time at which the fluctuation does not occur in the gate signal. That is, a luminance difference may occur due to the fluctuation of the gate signal. Embodiments provide a display device capable of reducing or preventing a luminance difference due to a fluctuation of a gate signal. In accordance with an embodiment of the disclosure, a display device includes: a first gate power line, a second gate power line, and a third gate power line, each of which is applied with a first voltage, the first gate power line, the second gate power line, and the third gate power line, where the first gate power line, the second gate power line, and the third gate power line extend to be spaced apart from each other; and a first gate driver including a plurality of stages which outputs a plurality of gate signals. In such an embodiment, each of a first stage and a second stage among the plurality of stages includes a plurality of transistors and a capacitor which are connected to each other, and the first stage and the second stage have a same structure as each other. In such an embodiment, a first electrode of a first transistor in the first stage is connected to the first gate power line, a second electrode of the first transistor in the first stage is connected to an output terminal of the first stage, a first electrode of a first transistor in the second stage is connected to the second gate power line, and a second electrode of the first transistor in the second stage is connected to an output terminal of the second stage. In an embodiment, each of the first stage and the second stage may further include a second transistor including a first electrode connected to the third gate power line. In an embodiment, the display device may further include a reference gate power line. In such an embodiment, the first stage further may include a pull-down transistor including a first electrode connected to the output terminal and a second electrode connected to the reference gate power line. In an embodiment, the display device may further include a first clock signal line, a second clock signal line, and a start signal line. In such an embodiment, the first stage may further include: a zeroth transistor including a first electrode connected to the start signal line or an output unit of a previous stage, a second electrode, and a gate electrode connected to the first clock signal line; a third transistor including a first electrode connected to a second electrode of the second transistor, a second electrode connected to the second clock signal line, and a gate electrode connected to a gate electrode of the pull-down transistor; a fourth transistor including a first electrode connected to a gate electrode of the second transistor, a second electrode connected to the first clock signal line, and a gate electrode connected to the second electrode of the zeroth transistor; a fifth transistor including a first electrode connected to the first electrode of the fourth transistor, a second electrode connected to the reference gate power line, and a gate electrode connected to the first clock signal line; a first coupling transistor including a f