US-12626672-B2 - Array substrate, display apparatus and control method thereof

US12626672B2US 12626672 B2US12626672 B2US 12626672B2US-12626672-B2

Abstract

An array substrate has a display area and a bonding region. The display area includes a distal region, a proximal region, and a middle region therebetween. The array substrate includes a base, a common electrode located in the display area, a connecting lead disposed outside the distal region, a conductive frame at least partially surrounding the display area, and at least one first common signal line, at least one second common signal line and at least one third common signal line. The first common signal line, the second common signal line and the third common signal line are respectively coupled to portions of the common electrode located in the distal region, the proximal region and the middle region. The first common signal line is coupled to the connecting lead. The connecting lead and the portion of the common electrode located in the distal region are coupled to the conductive frame.

Inventors

Xiao Wang
Yan Yan
Yu Ma

Assignees

BEIJING BOE DISPLAY TECHNOLOGY CO., LTD.
BOE TECHNOLOGY GROUP CO., LTD.

Dates

Publication Date: 20260512
Application Date: 20250117
Priority Date: 20200311

Claims (19)

1 . An array substrate having a display area and a bonding region located at a side of the display area; the display area including gate lines extending in a first direction and arranged in a second direction, the first direction intersecting the second direction; the bonding region corresponding to a first region, the first region extending in the first direction; the array substrate further having a second region, a third region and a fourth region, the second region extending in the first direction; the first region and the second region being opposite in the second direction, and the third region and the fourth region being opposite in the first direction; the display area being located between the first region and the second region and between the third region and the fourth region; the display area including a distal region away from the bonding region and a proximal region proximate to the bonding region; the array substrate comprising: a base; a common electrode disposed on the base and located in the display area; at least one first common signal line disposed on the base; the at least one first common signal line being disposed in the third region and/or the fourth region; the at least one first common signal line being coupled to the common electrode; a connecting lead disposed in the second region; the at least one first common signal line being coupled to the connecting lead; and a conductive frame, at least part of the conductive frame being located in the second region; the connecting lead and the common electrode being coupled to the conductive frame, so that the at least one first common signal line is coupled to the common electrode through the connecting lead and the conductive frame; wherein the connecting lead includes at least two first connecting lines, and the at least two first connecting lines are coupled to the conductive frame; the display area further includes a pixel electrode and a thin film transistor, and the pixel electrode is couple to the thin film transistor; and the conductive frame is further located in the third region; the array substrate further comprises a plurality of second connecting lines located on a side of the common electrode proximate to the third region, and the conductive frame is coupled to the common electrode through the plurality of second connecting lines.
2 . The array substrate according to claim 1 , wherein the conductive frame is further located in the fourth region; the array substrate further comprises a plurality of third connecting lines located on a side of the common electrode proximate to the fourth region, and the conductive frame is coupled to the common electrode through the plurality of third connecting lines.
3 . The array substrate according to claim 2 , wherein the plurality of second connecting lines and the plurality of third connecting lines are disposed symmetrically about a midline of the display area in the second direction.
4 . The array substrate according to claim 1 , further comprising at least one second common signal line disposed on the base; the at least one second common signal line being disposed in the third region and/or the fourth region; the at least one second common signal line being coupled to the common electrode.
5 . The array substrate according to claim 4 , further comprising at least one third common signal line disposed on the base; the at least one third common signal line being disposed in the third region and/or the fourth region, and a third common signal line being disposed between a first common signal line and the display area; wherein the display area further includes a middle region located between the distal region and the proximal region; the at least one first common signal line is coupled to a portion of the common electrode located in the distal region and extending to the bonding region; the at least one second common signal line is coupled to a portion of the common electrode located in the proximal region and extending to the bonding region; and the at least one third common signal line is coupled to a portion of the common electrode located in the middle region and extending to the bonding region.
6 . The array substrate according to claim 5 , further comprising at least one feedback signal line disposed on the base; the at least one feedback signal line being coupled to the portion of the common electrode located in the distal region and extending to the bonding region, and a feedback signal line being disposed between the first common signal line and the third common signal line; wherein the feedback signal line in the at least one feedback signal line is configured to transmit a common voltage signal of the portion of the common electrode located in the distal region.
7 . The array substrate according to claim 6 , wherein the at least one feedback signal line includes two feedback signal lines, and the two feedback signal lines are disposed in the third region and the fourth region, respectively.
8 . The array substrate according to claim 4 , wherein the at least one second common signal line includes two second common signal lines, and the two second common signal lines are disposed at two opposite ends of a side of the proximal region proximate to the bonding region.
9 . The array substrate according to claim 5 , wherein the at least one third common signal line includes two third common signal lines, and the two third common signal lines are disposed on two opposite sides of the display area.
10 . The array substrate according to claim 6 , wherein the at least one feedback signal line and the at least one first common signal line are made of a same material and disposed in a same layer; and/or the at least one feedback signal line is coupled to the conductive frame, so that the at least one feedback signal line is coupled to the portion of the common electrode located in the distal region through the conductive frame.
11 . The array substrate according to claim 6 , wherein a resistance of the first common signal line, a resistance of the second common signal line, and a resistance of the third common signal line are all less than or equal to 300Ω; and a resistance of the feedback signal line is less than or equal to 1000Ω.
12 . The array substrate according to claim 1 , wherein the connecting lead and the portion of the common electrode located in the distal region are coupled to the conductive frame, so that the at least one first common signal line is coupled to the portion of the common electrode located in the distal region through the connecting lead and the conductive frame.
13 . The array substrate according to claim 1 , wherein the at least one first common signal line includes two first common signal lines, and the two first common signal lines are disposed in the third region and the fourth region, respectively.
14 . The array substrate according to claim 1 , wherein the at least one first common signal line, the connecting lead and the conductive frame are made of a same material and disposed in a same layer.
15 . The array substrate according to claim 1 , further comprising: data lines disposed on the base, the data lines being arranged closer to the base than the common electrode in a direction perpendicular to the base; wherein orthogonal projections of the data lines on the base at least partially overlap with an orthogonal projection of the common electrode on the base.
16 . The array substrate according to claim 1 , wherein the array substrate has a plurality of sub-pixel regions; the common electrode includes a plurality of sub-electrodes and a plurality of first conductive patterns; and a sub-electrode is located in at least one sub-pixel region, and adjacent sub-electrodes are coupled through at least one first conductive pattern.
17 . A display apparatus, comprising: the array substrate according to claim 1 ; and a circuit board bonded to the bonding region in the array substrate; the circuit board including a control circuit, and the control circuit being coupled to the first common signal line in the array substrate; wherein the control circuit is configured to, according to a common voltage signal of the portion of the common electrode located in the distal region, generate a first compensation common voltage signal and transmit the first compensation common voltage signal to the first common signal line.
18 . The display apparatus according to claim 17 , wherein the array substrate further includes at least one feedback signal line disposed on the base; the at least one feedback signal line is coupled to the portion of the common electrode located in the distal region, and the at least one feedback signal line extends to the bonding region and is configured to be coupled to the circuit board; wherein a feedback signal line in the at least one feedback signal line is configured to transmit the common voltage signal of the portion of the common electrode located in the distal region to the circuit board.
19 . The display apparatus according to claim 17 , wherein the array substrate further includes at least one second common signal line and at least one third common signal line that are disposed on the base; the at least one second common signal line is disposed in the third region and/or the fourth region, and the at least one second common signal line is coupled to a portion of the common electrode located in the proximal region; the at least one third common signal line is disposed in the third region and/or the fourth region, and the at least one third common signal line is coupled to a portion of the common electrode located in a middle region between the distal region and the proximal region; and the control circuit is further configured to, according to the common voltage signal, generate a second compensation common voltage signal and transmit the second compensation common voltage signal to the second common signal line, and generate a third compensation common voltage signal and transmit the third compensation common voltage signal to the third common signal line.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application is a continuation of U.S. patent application Ser. No. 18/626,983, filed on Apr. 4, 2024, which is a continuation of U.S. patent application Ser. No. 18/191,628, filed on Mar. 28, 2023, which is a continuation of U.S. patent application Ser. No. 17/425,204, filed on Jul. 22, 2021, which is a national phase entry under 35 USC 371 of International Patent Application No. PCT/CN2020/140386, filed on Dec. 28, 2020, which in turn claims priority to Chinese Patent Application No. 202010167374.8, filed on Mar. 11, 2020, which are incorporated herein by reference in their entirety. TECHNICAL FIELD The present disclosure relates to the field of display technologies, and in particular, to an array substrate, a display apparatus and a control method thereof. BACKGROUND In recent years, with the advancement of display technologies, users have higher and higher requirements for viewing experience. Liquid crystal display technology has been successfully applied to display products such as notebook computers, display screens, and televisions. With an increase in the possession of liquid crystal display products, people have also put forward higher requirements for display quality of liquid crystal display products. SUMMARY In an aspect, an array substrate is provided. The array substrate has a display area and a bonding region located at a side of the display area. The display area includes gate lines extending in a first direction and arranged in a second direction, the first direction intersects the second direction. The bonding region corresponds to a first region, and the first region extends in the first direction. The array substrate further has a second region, a third region and a fourth region. The second region extends in the first direction. The first region and the second region are opposite in the second direction, and the third region and the fourth region are opposite in the first direction. The display area is located between the first region and the second region and between the third region and the fourth region. The display area includes a distal region away from the bonding region and a proximal region proximate to the bonding region. The array substrate includes: a base, a common electrode disposed on the base and located in the display area, a connecting lead disposed in the second region, a conductive frame, and at least one first common signal line disposed on the base. The at least one first common signal line is disposed in the third region and/or the fourth region, and is coupled to the common electrode. The at least one first common signal line is coupled to the connecting lead. At least part of the conductive frame is located in the second region. The connecting lead and the common electrode are coupled to the conductive frame, so that the at least one first common signal line is coupled to the common electrode through the connecting lead and the conductive frame. The connecting lead includes at least two first connecting lines, and the at least two first connecting lines are coupled to the conductive frame. The display area further includes a pixel electrode and a thin film transistor, and the pixel electrode is couple to the thin film transistor. In some embodiments, the conductive frame is further located in the third region. The array substrate further includes a plurality of second connecting lines located on a side of the common electrode proximate to the third region, and the conductive frame is coupled to the common electrode through the plurality of second connecting lines. In some embodiments, the conductive frame is further located in the fourth region. The array substrate further includes a plurality of third connecting lines located on a side of the common electrode proximate to the fourth region, and the conductive frame is coupled to the common electrode through the plurality of third connecting lines. In some embodiments, the plurality of second connecting lines and the plurality of third connecting lines are disposed symmetrically about a midline of the display area in the second direction. In some embodiments, the array substrate further includes at least one second common signal line disposed on the base. The at least one second common signal line is disposed in the third region and/or the fourth region; and the at least one second common signal line is coupled to the common electrode. In some embodiments, the array substrate further includes at least one third common signal line disposed on the base. The at least one third common signal line is disposed in the third region and/or the fourth region, and a third common signal line is disposed between a first common signal line and the display area. The display area further includes a middle region located between the distal region and the proximal region. The at least one first common signal line is coupled to a portion of the common electrode located in the distal region