US-12626731-B2 - Methods for optimizing semiconductor device placement on a substrate for improved performance, and associated systems and methods

Abstract

Methods of optimizing the placement of memories in a memory device including a substrate and an electrical component, and associated devices and systems, are disclosed herein. A representative method includes first testing the memories to determine at least one parameter for each of the memories indicating an ability of the memory to process signals from the electrical component. The method can further include labeling each memory with a label based on the parameter, the labels including at least a first label and a second label. The first label can indicate that the memories with the first label are better able to process signals from the electrical component than the memories with the second label. The method can further include electrically coupling the memories to the substrate such that the memories with the second label are positioned closer to the electrical component than the memories with the first label.

Inventors

• James S. Rehmeyer
• Christopher G. Wieduwilt

Assignees

• MICRON TECHNOLOGY, INC.

Dates

Publication Date

20260512

Application Date

20240202

Claims (20)

1. 1 . A memory device, comprising: a printed circuit board (PCB) having a planar surface; an electrical component coupled to the PCB; and a plurality of memories mounted on the planar surface of the PCB and electrically coupled to the electrical component via the PCB, wherein the plurality of memories has a matching design and specification and is configured to directly utilize a common voltage source and a common clock source, wherein the plurality of memories includes a first group of memories and a second group of memories according to performance variations, wherein the first group of memories are positioned farthest across the planar surface from the electrical component and the second group of memories are closer to the electrical component, wherein each memory in the plurality of the memories is a semiconductor package and has a performance parameter that corresponds to an ability of the memory to process (1) received power signals, (2) received command, address, and/or clock signals, (3) data signals, or a combination thereof, and wherein the performance parameter of the memories in the first group is greatest amongst the plurality of memories; wherein the memory device comprises a memory module.
2. 2 . The memory device of claim 1 wherein the electrical component is electrically coupled to a center of the PCB wherein the second group of memories is coupled to the PCB adjacent to the electrical component, and wherein he first group of memories is coupled to the PCB laterally outboard of the memories in the second group of memories.
3. 3 . The memory device of claim 1 wherein the performance parameter of the memories in the first group is greater than the performance parameter of the memories in the second group due to variations in a manufacturing process used to manufacture the memories.
4. 4 . The memory device of claim 1 wherein the electrical component is a power management integrated circuit (PMIC).
5. 5 . The memory device of claim 4 wherein the performance parameter corresponds to a current level of each of the memories.
6. 6 . The memory device of claim 4 wherein the performance parameter is a threshold voltage level of each of the memories.
7. 7 . The memory device of claim 4 wherein the performance parameter is a power and/or speed performance parameter of each of the memories.
8. 8 . The memory device of claim 4 wherein the performance parameter of the memories in the first group of memories comprises a fast-fast (FF) process corner, and wherein the performance parameter of the memories in the second group of memories comprises a slow-slow (SS) process comer.
9. 9 . The memory device of claim 1 wherein the electrical component is a registered clock driver (RCD).
10. 10 . The memory device of claim 9 wherein the performance parameter is at least one of a setup time, a hold time, and a setup-hold margin of each of the memories.
11. 11 . The memory device of claim 1 wherein the electrical component is an edge connector of the PCB.
12. 12 . The memory device of claim 11 wherein the performance parameter is at least one of a setup time, a hold time, a setup-hold margin, an edge rate, a data eye height, and a data eye width of each of the memories.
13. 13 . A method of optimizing the placement of memories in a memory device-module including a printed circuit board (PCB) substrate and an electrical component electrically coupled to the substrate, the method comprising: testing the memories to determine at least one parameter for each of the memories, wherein the at least one parameter indicates an ability of the memory to process signals from the electrical component, wherein the memories have a matching design and specification and the at least one parameter corresponds to variations within the matching design and specification, wherein the memories are configured to directly utilize a common voltage source and a common clock source; grouping the tested memories according to the determined parameter, wherein resulting groupings include at least a first group of memories and a second group of memories, and wherein the first grouping of memories best amongst the tested memories in processing signals from the electrical component and after grouping the memories, mounting the memories on a planar surface of the PCB substrate according to the groupings such that the second group of memories are positioned closer to the electrical component across the planar surface and the first group of memories are located farthest away from the electrical component.
14. 14 . The method of claim 13 wherein the electrical component is electrically coupled to a center of the PCB substrate, wherein the memories in the second group are coupled to the PCB substrate adjacent to the electrical component, and wherein the memories in the first group are coupled to the PCB substrate laterally outboard of the memories with the second group.
15. 15 . The method of claim 13 wherein the electrical component is a power management integrated circuit (PMIC), and wherein the parameter includes a current level of each the memories.
16. 16 . The method of claim 13 wherein the electrical component is a power management integrated circuit (PMIC), and wherein the parameter is a threshold voltage level of each of the memories.
17. 17 . The method of claim 13 wherein the electrical component is a power management integrated circuit (PMIC), and wherein the parameter is a power and/or speed performance parameter of each of the memories.
18. 18 . The method of claim 13 wherein the electrical component is a power management integrated circuit (PMIC), and wherein the first group of memories correspond to a fast-fast (FF) process corner, and wherein the second group of memories correspond to a slow-slow (SS) process corner.
19. 19 . The method of claim 13 wherein the electrical component is a registered clock driver (RCD), and wherein the parameter is at least one of a setup time, a hold time, and a setup-hold margin of each of the memories.
20. 20 . The method of claim 13 wherein the electrical component is an edge connector of the PCB substrate, and wherein the parameter is at least one of a setup time, a hold time, a setup-hold margin, an edge rate, a data eye height, and a data eye width of each of the memories.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application is a continuation of U.S. patent application Ser. No. 17/718,200, filed Apr. 11, 2022, now U.S. Pat. No. 11,929,139, which claims priority to U.S. Provisional Patent Application No. 63/238,467, filed Aug. 30, 2021, each of which is incorporated herein by reference in its entirety. TECHNICAL FIELD The present disclosure generally relates to methods for optimizing the placement of semiconductor devices, such as memory devices, on a substrate for improved performance. BACKGROUND Memory packages or modules typically include multiple memory devices mounted on a substrate. Memory devices are widely used to store information related to various electronic devices such as computers, wireless communication devices, cameras, digital displays, and the like. Information is stored by programing different states of a memory cell. Various types of memory devices exist, including magnetic hard disks, random access memory (RAM), read only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), and others. Improving memory packages, generally, may include increasing memory cell density, increasing read/write speeds or otherwise reducing operational latency, increasing reliability, increasing data retention, reducing power consumption, reducing manufacturing costs, and reducing the size or footprint of the memory packages and/or components of the memory devices, among other metrics. BRIEF DESCRIPTION OF THE DRAWINGS Many aspects of the present technology can be better understood with reference to the following drawings. The components in the drawings are not necessarily to scale. Instead, emphasis is placed on illustrating clearly the principles of the present technology. FIG. 1A is a partially schematic front view of a memory device in accordance with embodiments of the present technology. FIGS. 1B and 1C are partially schematic back views of the memory device of FIG. 1A in accordance with embodiments of the present technology. FIG. 2 is a flow diagram of a process or method for optimizing the placement of memories in the memory device of FIGS. 1A-1C in accordance with embodiments of the present technology. FIGS. 3A and 3B are front and back views, respectively, illustrating the optimized positioning of memories in the memory device of FIGS. 1A-1C in accordance with embodiments of the present technology. FIGS. 4A and 4B are front and back views, respectively, illustrating the optimized positioning of memories in the memory device of FIGS. 1A-1C in accordance with additional embodiments of the present technology. FIG. 5 is a flow diagram of a process or method for optimizing the placement of memories in the memory device of FIGS. 1A-1C in accordance with additional embodiments of the present technology. FIG. 6 is a flow diagram of a process or method for optimizing the placement of memories in the memory device of FIGS. 1A-1C in accordance with additional embodiments of the present technology. FIGS. 7A and 7B are front and back views, respectively, illustrating the optimized positioning of memories in the memory device of FIGS. 1A-1C in accordance with additional embodiments of the present technology. FIG. 8 is a flow diagram of a process or method for optimizing the placement of memories in the memory device of FIGS. 1A-1C in accordance with additional embodiments of the present technology. FIG. 9 is a flow diagram of a process or method for optimizing the placement of memories in the memory device of FIGS. 1A-1C in accordance with additional embodiments of the present technology. FIG. 10 is a schematic view of a system that includes a memory device in accordance with embodiments of the present technology. DETAILED DESCRIPTION Embodiments of the present technology are directed to methods for optimizing the placement of memories in a memory device (e.g., a dual in-line memory module (DIMM)) for improved performance, and associated systems and devices. In several of the embodiments described below, the memory device includes a substrate and an electrical component coupled to the substrate. A method for optimizing the placement of the memories along the substrate can include first testing the memories to determine at least one parameter for each of the memories indicating an ability of the memory to process signals from the electrical component. The method can further include labeling each memory with a label based on the parameter, the labels including at least a first label and a second label. The first label can indicate that the memories with the first label are better able to process signals from the electrical component than the memories with the second label. The method can further include electrically coupling the memories to the substrate such that the memories with the second label are positioned closer to the electrical component than the memories with the first label. In some embodiments, the electrical component can be a power management integrated