US-12626732-B2 - Semiconductor structure including memory signal transmission line in backside redistribution

Abstract

A semiconductor structure includes a substrate, a data storage element, and first and second bit line sets. The substrate has a front side and a backside and includes a substrate layer, a first active layer, and a second active layer. The second active layer is proximal to the front side. The substrate layer is proximal to the backside. The data storage element extends across the first and second active layers. The first bit line set includes a first bit line and a first complementary bit line. At least one of the first bit line and the first complementary bit line is disposed on the front side of the substrate. The second bit line set includes a second bit line and a second complementary bit line. At least one of the second bit line and the second complementary bit line is disposed on the backside of the substrate.

Inventors

• ZE-XIAN LU
• PO-HSUN CHU
• BO WEI WU
• Jung-Hsuan Chen

Assignees

• TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Dates

Publication Date

20260512

Application Date

20240227

Claims (20)

1. 1 . A semiconductor structure, comprising: a substrate, having a front side and a backside opposite to the front side, wherein the substrate includes a substrate layer, a first active layer disposed above the substrate layer, and a second active layer disposed above the first active layer, the second active layer is proximal to the front side, and the substrate layer is proximal to the backside; a data storage element, disposed in and surrounding the first active layer and the second active layer; a first bit line set, including a first bit line and a first complementary bit line, wherein at least one of the first bit line and the first complementary bit line is disposed on the front side of the substrate above the second active layer; and a second bit line set, including a second bit line and a second complementary bit line, wherein at least one of the second bit line and the second complementary bit line is disposed on the backside of the substrate below the substrate layer, wherein the first bit line set further includes a third bit line coupled to the first bit line, and the third bit line is disposed on a side of the substrate opposite to the first bit line.
2. 2 . The semiconductor structure of claim 1 , wherein the data storage element is a static random-access memory (SRAM) device.
3. 3 . The semiconductor structure of claim 1 , wherein the first bit line and the second bit line are disposed on the front side of the substrate above the second active layer, and the first complementary bit line and the second complementary bit line are disposed on the backside of the substrate below the substrate layer.
4. 4 . The semiconductor structure of claim 1 , wherein the first bit line and the first complementary bit line are disposed on the front side of the substrate above the second active layer, and the second bit line and the second complementary bit line are disposed on the backside of the substrate below the substrate layer.
5. 5 . The semiconductor structure of claim 1 , wherein the second bit line set further includes a fourth bit line coupled to the second bit line, and the fourth bit line is disposed on a side of the substrate opposite to the second bit line.
6. 6 . The semiconductor structure of claim 1 , further comprising: a power/ground line, disposed on the backside of the substrate below the substrate layer at an elevation same as that of the at least one of the second bit line and the second complementary bit line.
7. 7 . The semiconductor structure of claim 6 , wherein the first bit line and the second bit line are disposed on the backside of the substrate below the substrate layer, and the power/ground line is disposed between the first bit line and the second bit line.
8. 8 . The semiconductor structure of claim 1 , wherein the data storage element includes a transistor, and the power/ground line is connected to a source of the transistor from the backside of the substrate, and the at least one of the second bit line or the second complementary bit line is connected to a drain of the transistor from the backside of the substrate.
9. 9 . The semiconductor structure of claim 1 , wherein the data storage element includes a transistor having a source, a gate and a drain arranged along a first direction, and the first bit line or the first complementary bit line extends substantially along the first direction.
10. 10 . A semiconductor structure, comprising: a substrate, having a front side and a backside opposite to the front side, wherein the substrate includes a substrate layer, a first active layer disposed above the substrate layer, and a second active layer disposed above the first active layer, the second active layer is proximal to the front side, and the substrate layer is proximal to the backside; a data storage element, disposed in and surrounding the first active layer and the second active layer; a first word line, disposed on the backside of the substrate below the substrate layer; and a second word line, disposed on the front side of the substrate above the second active layer.
11. 11 . The semiconductor structure of claim 10 , further comprising: a power/ground line, disposed on the backside of the substrate below the substrate layer, wherein the power/ground line is disposed at an elevation above an elevation of the first word line.
12. 12 . The semiconductor structure of claim 11 , wherein an extending direction of the power/ground line is substantially perpendicular to an extending direction of the first word line.
13. 13 . The semiconductor structure of claim 10 , further comprising: a third word line, disposed on the front side of the substrate at an elevation higher than an elevation of the second word line.
14. 14 . A semiconductor structure, comprising: a substrate, having a front side and a backside opposite to the front side, wherein the substrate includes a substrate layer proximal to the backside; a plurality of complementary FETs (CFETs), disposed on the substrate layer, wherein the CFETs are proximal to the front side of the substrate and collectively correspond to a data storage element; a first bit line set, including a first bit line and a first complementary bit line, wherein at least one of the first bit line and the first complementary bit line is disposed on the front side of the substrate above the CFETs; a second bit line set, including a second bit line and a second complementary bit line, wherein at least one of the second bit line and the second complementary bit line is disposed on the backside of the substrate below the substrate layer; a first power/ground line, disposed on the backside of the substrate below the substrate layer at an elevation same as an elevation of the at least one of the second bit line and the second complementary bit line; and a first word line, disposed on the front side of the substrate above the at least one of the first bit line and the first complementary bit line.
15. 15 . The semiconductor structure of claim 14 , further comprising: a second power/ground line, disposed on the front side of the substrate above the CFETs at an elevation same as an elevation of the at least one of the first bit line and the first complementary bit line.
16. 16 . The semiconductor structure of claim 14 , further comprising: a second word line, disposed on the backside of the substrate below the substrate layer, wherein the second word line is at an elevation below the elevation of the first power/ground line.
17. 17 . The semiconductor structure of claim 14 , wherein the at least one of the second bit line and the second complementary bit line disposed on the backside of the substrate includes a first metallic material different from a second metallic material of the at least one of the first bit line and the first complementary bit line disposed on the front side of the substrate, and a resistance of the first metallic material is substantially less than a resistance of the second metallic material.
18. 18 . The semiconductor structure of claim 1 , wherein a material of the first bit line set is different from a material of the second bit line set.
19. 19 . The semiconductor structure of claim 10 , wherein the data storage element is a static random-access memory (SRAM) device.
20. 20 . The semiconductor structure of claim 14 , wherein a material of the first bit line set is different from a material of the second bit line set.

Description

BACKGROUND The semiconductor integrated circuit industry has experienced rapid growth in recent years. Technological advances in semiconductor materials and design have produced increasingly compact and complex circuits. Such material and design advances have been made possible as technologies related to processing and manufacturing have also undergone technical advances. As the semiconductor industry has progressed into advanced technology process nodes in pursuit of smaller product scales and multiple functions, various approaches have been studied and obstacles of electrical resistance and coupling effect of signals of a memory device have been encountered. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. FIG. 1 is a schematic 3D diagram of a semiconductor structure in accordance with some embodiments of the present disclosure. FIG. 2 is a schematic cross-sectional diagram of the semiconductor structure of FIG. 1 along a line A-A′ in accordance with some embodiments of the present disclosure. FIG. 3 is a schematic 3D diagram of a semiconductor structure in accordance with some embodiments of the present disclosure. FIG. 4 is a schematic cross-sectional diagram of the semiconductor structure of FIG. 3 along a line B-B′ in accordance with some embodiments of the present disclosure. FIGS. 5 to 13 are schematic 3D diagrams of semiconductor structures for illustrations of different arrangements of signal lines in order to achieve a data storage device in accordance with different embodiments of the present disclosure. FIG. 14 is a schematic 3D diagram of a semiconductor structure in accordance with some embodiments of the present disclosure. FIG. 15 is a schematic top-view perspective of the semiconductor structure shown in FIG. 14 in accordance with some embodiments of the present disclosure. FIG. 16 is a schematic bottom-view perspective of the semiconductor structure shown in FIG. 14 in accordance with some embodiments of the present disclosure. DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of elements and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “over,” “upper,” “on” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. As used herein, although the terms such as “first,” “second” and “third” describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms may be only used to distinguish one element, component, region, layer or section from another. The terms such as “first,” “second” and “third” when used herein do not imply a sequence or order unless clearly indicated by the context. In addition, the term “source/drain region” or “source/drain regions” may refer to a source or a drain, individually or collectively dependent upon the context. Notwithstanding that the numerical ranges and parameters setting forth the broad scope of the disclosure are approximations, the numerical values set forth in the specific examples are reported as precisely as possible. Any numerical value, however, inherently contains certain errors necessarily resulting from normal deviation found in the respective testing measurements. Also, as used he