US-12626733-B2 - Power management integrated circuit and memory module including the same

US12626733B2US 12626733 B2US12626733 B2US 12626733B2US-12626733-B2

Abstract

A power management integrated circuit includes an internal output transistor connected to an external voltage input line, to which an external voltage is supplied, and outputting an internal output voltage, a self-overvoltage protection circuit detecting whether the external voltage exceeds a breakdown condition for the internal output transistor and providing a gate voltage to a gate terminal of the internal output transistor and a clamp circuit outputting, as the internal output voltage, a first clamp voltage having a uniform level in a first overvoltage clamp mode and a second clamp voltage, which is leveled down from the external voltage, in a second overvoltage clamp mode. When the internal output transistor is turned off, the clamp circuit outputs the internal output voltage. The external voltage in the second overvoltage clamp mode may be greater than the external voltage in the first overvoltage clamp mode.

Inventors

Jae Hyun Park
Dong Woo BAEK
Hyeung Joon CHA

Assignees

SAMSUNG ELECTRONICS CO., LTD.

Dates

Publication Date: 20260512
Application Date: 20240619
Priority Date: 20231116

Claims (20)

1 . A power management integrated circuit (PMIC) comprising: an internal output transistor connected to an external voltage input line, to which an external voltage is supplied, and configured to output an internal output voltage; a self-overvoltage protection circuit configured to: detect whether the external voltage exceeds a breakdown condition for the internal output transistor, and provide a gate voltage to a gate terminal of the internal output transistor; and a clamp circuit configured to output, as the internal output voltage: a first clamp voltage having a uniform level in a first overvoltage clamp mode, and a second clamp voltage, which is leveled down from the external voltage, in a second overvoltage clamp mode, wherein when the internal output transistor is turned off, the PMIC is configured such that the clamp circuit outputs the internal output voltage, and wherein a level of the external voltage in the second overvoltage clamp mode is greater than a level of the external voltage in the first overvoltage clamp mode.
2 . The PMIC of claim 1 , wherein the self-overvoltage protection circuit includes: a first Zener diode and a first resistor, which are connected in series between the external voltage input line and a first node, second and third resistors, which are connected in series between the first node and a ground voltage line, a fourth resistor connected between the external voltage input line and a second node, and configured to convert the external voltage into a sensed external voltage, and a second Zener diode connected between the second node and the ground voltage line, and wherein a sum of resistances of the second and third resistors is greater than a resistance of the first resistor.
3 . The PMIC of claim 2 , wherein the self-overvoltage protection circuit further includes: a fifth resistor connected between the second node and a third node, a first low-voltage transistor connected between the third node and the ground voltage line, a first inverter configured to invert a signal from the third node and output the inverted signal from the third node to a fourth node, and a second inverter configured to invert a signal from the fourth node and output the inverted signal from the fourth node to a fifth node.
4 . The PMIC of claim 3 , wherein the self-overvoltage protection circuit further includes: a sixth resistor having a first end and a second end connected to the ground voltage line, a seventh resistor connected between the external voltage input line and a sixth node, a second low-voltage transistor connected between the sixth node and the first end of the sixth resistor, and including a gate terminal connected to the fourth node, and a third low-voltage transistor connected between the ground voltage line and a common node of the second and third resistors, and including a gate terminal connected to the fifth node.
5 . The PMIC of claim 4 , wherein the self-overvoltage protection circuit further includes: a fourth low-voltage transistor connected between the external voltage input line and a seventh node, and including a gate terminal connected to the sixth node, an eighth resistor connected between the external voltage input line and the seventh node, and a high-voltage sensing transistor connected between the seventh node and the ground voltage line, and including a gate terminal connected to the fifth node, and wherein the gate terminal of the internal output transistor is connected to the seventh node.
6 . The PMIC of claim 1 , wherein the clamp circuit further includes: a fifth Zener diode, a tenth resistor, a first high-voltage clamp transistor, a ninth resistor, and a fourth Zener diode, which are connected in series between the external voltage input line and a ground voltage line, an eleventh resistor connected between the external voltage input line and a drain terminal of the first high-voltage clamp transistor, and a second high-voltage clamp transistor connected between the external voltage input line and an eighth node configured to output the internal output voltage, and wherein a gate terminal and the drain terminal of the first high-voltage clamp transistor and a gate terminal of the second high-voltage clamp transistor are connected to a ninth node.
7 . A power management integrated circuit (PMIC) comprising: an internal output transistor including a source terminal connected to an external voltage input line, to which an external voltage is supplied, and configured to output an internal output voltage to a voltage supply terminal of an external device in a normal mode and an overvoltage sensing mode; a self-overvoltage protection circuit configured to: turn on the internal output transistor in the overvoltage sensing mode, and turn off the internal output transistor in a clamp mode; and a clamp circuit including first and second high-voltage clamp transistors, which are connected to each other via a current mirror, and configured to output a clamp voltage as the internal output voltage, which is generated from the second high-voltage clamp transistor to the external device, in the clamp mode, wherein when the external voltage becomes higher than a first voltage, the PMIC is configured such that the self-overvoltage protection circuit turns on the internal output transistor, and wherein when the external voltage becomes higher than a second voltage greater than the first voltage, the PMIC is configured such that the self-overvoltage protection circuit turns off the internal output transistor.
8 . The PMIC of claim 7 , wherein the self-overvoltage protection circuit includes: a first Zener diode and first, second, and third resistors, which are connected in series between the external voltage input line and a ground voltage line, a fourth resistor and a second Zener diode, which are connected in series between the external voltage input line and the ground voltage line, a third Zener diode connected between the ground voltage line and a first node that is a common node of the first and second resistors, and a first low-voltage transistor including a gate terminal connected to the first node.
9 . The PMIC of claim 8 , wherein the self-overvoltage protection circuit further includes: a fifth resistor connected between a second node that is a common node of the fourth resistor and the second Zener diode and a third node to which a drain terminal of the first low-voltage transistor is connected, a first inverter supplied with a power from the second node, configured to invert a signal from the third node, and to output the inverted signal from the third node to a fourth node, a second inverter supplied with a power from the second node, configured to invert a signal from the fourth node, and to output the inverted signal from the fourth node to a fifth node, and a seventh resistor, a second low-voltage transistor, and a sixth resistor, which are connected in series between the external voltage input line and the ground voltage line, wherein a gate terminal of the second low-voltage transistor is connected to the fourth node.
10 . The PMIC of claim 9 , wherein the self-overvoltage protection circuit further includes: a third low-voltage transistor connected between the ground voltage line and a common node of the second and third resistors, and including a gate terminal connected to the fifth node, a fourth low-voltage transistor connected between the external voltage input line and a seventh node, the fourth low-voltage transistor including a gate terminal connected to a sixth node that is a common node of the seventh resistor and the second low-voltage transistor, and a high-voltage sensing transistor connected between the seventh node and the ground voltage line, and including a gate terminal connected to the fifth node.
11 . The PMIC of claim 10 , further comprising: an eighth resistor connected between the external voltage input line and the seventh node, wherein a gate terminal of the internal output transistor is connected to the seventh node, and wherein the internal output transistor is configured to turn on or turn off based on a level of the external voltage.
12 . The PMIC of claim 10 , wherein the first to third Zener diodes are configured to turn on in response to first to third Zener voltages, respectively, and wherein when the external voltage becomes higher than the second voltage, the PMIC is configured such that the high-voltage sensing transistor and the internal output transistor are turned off and the first and fourth low-voltage transistors are turned on, in the clamp mode.
13 . The PMIC of claim 8 , wherein the first to third Zener diodes are configured to turn on in response to first to third Zener voltages, respectively, and wherein the first voltage is identical to each of the first to third Zener voltages.
14 . The PMIC of claim 8 , wherein a resistance of the first resistor is smaller than a resistance of sum of a resistance of the second resistor and a resistance of the third resistor.
15 . The PMIC of claim 8 , wherein the first to third Zener diodes are configured to turn on in response to first to third Zener voltages, respectively, and wherein when the external voltage is higher than the first Zener voltage of the first Zener diode and a sensed external voltage from the fourth resistor is higher than a second Zener voltage of the second Zener diode, the PMIC is configured such that the self-overvoltage protection circuit outputs the internal output voltage according to the external voltage by turning on the first and second Zener diodes and the internal output transistor, and turning off the third Zener diode, in the overvoltage sensing mode.
16 . The PMIC of claim 15 , wherein in the overvoltage sensing mode, the first high-voltage clamp transistor and second high-voltage clamp transistor are configured to be turned off.
17 . The PMIC of claim 8 , wherein the clamp circuit further includes: a fourth Zener diode and a ninth resistor, which are connected in series between the ground voltage line and a source terminal of the first high-voltage clamp transistor, a fifth Zener diode and a tenth resistor, which are connected in series between the external voltage input line and a drain terminal of the first high-voltage clamp transistor, and an eleventh resistor connected between the external voltage input line and the drain terminal of the first high-voltage clamp transistor, wherein the clamp circuit is configured to output the clamp voltage to the external device based on a state of the first high-voltage clamp transistor.
18 . The PMIC of claim 17 , wherein a resistance of the ninth resistor is identical to a resistance of the tenth resistor, and wherein a resistance of the eleventh resistor is greater than the resistance of the ninth resistor and the resistance of the tenth resistor.
19 . The PMIC of claim 17 , wherein the clamp mode includes a first overvoltage clamp mode and a second overvoltage clamp mode, wherein the fourth Zener diode is configured to be turned on and the fifth Zener diode is configured to be turned off, in the first overvoltage clamp mode, and wherein the fourth and fifth Zener diodes are configured to be both turned on in the second overvoltage clamp mode.
20 . A memory module comprising: memory input/output pins; a plurality of memory devices; and a power management integrated circuit (PMIC) configured to: receive an external voltage at an external voltage input line through at least one of the memory input/output pins, and output an internal output voltage to the plurality of memory devices, wherein the PMIC includes: an internal output transistor configured to turn on in a normal mode and an overvoltage sensing mode and provide the internal output voltage, and a clamp circuit including first and second high-voltage clamp transistors connected to each other via a current mirror, and configured to output a clamp voltage as the internal output voltage generated from the second high-voltage clamp transistor, wherein when the internal output transistor is turned off, the memory module is configured such that the clamp circuit outputs the clamp voltage from the second high-voltage clamp transistor.

Description

CROSS-REFERENCE TO RELATED APPLICATION(S) This application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2023-0159160 filed on Nov. 16, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference herein in its entirety. BACKGROUND 1. Field The present disclosure relates to a power management integrated circuit (PMIC) for a memory module. 2. Description of the Related Art Memory modules are powered by at least two external power sources in accordance with standard specifications. For example, the memory modules receive high-voltage power of 12V and low-voltage power of 5V or less, and convert them into internal voltages. In a memory system (e.g., a server module) that includes such memory modules, multiple memory modules are driven at the same time by a single server, so external power generated by the server is designed to drive high currents of tens of amperes (A) or greater. The power supply circuit of the server may have difficulties in applying a system that identifies the status of the parallel-connected memory modules and selectively controls the supplied currents, due to cost, power efficiency, and space constraints. In particular, there can be instances where a hot plug-short phenomenon occurs between high-voltage and low-voltage pins among the input/output pins of each memory module. A hot plug refers to a situation where memory modules are connected or disconnected while power is supplied during the operation of a server or a data center. In a hot-plug situation, if the connectors with the memory modules are defective or not properly connected, there are defective cables, or there are problems with the power supply device itself or compatibility issues with hardware components, a power short may occur between nodes that should not be electrically connected. This is referred to as a hot-plug short or the hot plug-short phenomenon. The hot plug-short phenomenon may lead to overcurrent, fire, or damage to memory modules and their connected memory system such as a server. For example, the burning of integrated circuits (ICs), known as ‘IC burnt,’ may occur due to damage to low-voltage devices connected to low-voltage pins, and the IC burnt of memory modules can be directly linked to fire hazards for the server. Therefore, there is a need for memory modules to have a feature that can protect them from unstable power supply conditions. SUMMARY Aspects of the present disclosure provide a memory module with improved durability and reliability, even in unstable power conditions. Aspects of the present disclosure also provide a power management integrated circuit (PMIC) that protects a memory module from a hot plug-short phenomenon. Aspects of the present disclosure also provide a memory device that includes a PMIC capable of operating stably while minimizing an increase in its area with the use of low-voltage devices. However, aspects of the present disclosure are not restricted to those set forth herein. The above and other aspects of the present disclosure will become more apparent to one of ordinary skill in the art to which the present disclosure pertains by referencing the detailed description of the present disclosure given below. According to an aspect of the present disclosure, there is provided a power management integrated circuit including an internal output transistor connected to an external voltage input line, to which an external voltage is supplied, and outputting an internal output voltage, a self-overvoltage protection circuit detecting whether the external voltage exceeds a breakdown condition for the internal output transistor and providing a gate voltage of the internal output transistor and a clamp circuit outputting, as the internal output voltage, a first clamp voltage with a uniform level in a first overvoltage clamp mode and a second clamp voltage, which is leveled down from the external voltage, in a second overvoltage clamp mode. When the internal output transistor is turned off, the clamp circuit may output the internal output voltage. The external voltage in the second overvoltage clamp mode may be greater than the external voltage in the first overvoltage clamp mode. According to another aspect of the present disclosure, there is provided a power management integrated circuit (PMIC) including an internal output transistor having a source terminal connected to an external voltage input line, to which an external voltage is supplied, and outputting an internal output voltage to a voltage supply terminal of an external device in a normal mode and an overvoltage sensing mode, a self-overvoltage protection circuit turning on the internal output transistor in the overvoltage sensing mode, and turning off the internal output transistor in clamp mode, and a clamp circuit including first and second high-voltage clamp transistors, which are connected to each other via a current mirror, and outputting a clamp voltage