US-12626735-B2 - Semiconductor memory device with voltage-controlled data latch node

US12626735B2US 12626735 B2US12626735 B2US 12626735B2US-12626735-B2

Abstract

A semiconductor memory device includes a sense amplifier provided between a memory cell array and an input/output circuit. The sense amplifier has a data latch circuit operating at a first operating voltage and having first and second nodes, a multiplexer operating at a second operating voltage, and a sense amplifier unit. The first node is connected to the multiplexer and latches a first voltage supplied from the multiplexer in accordance with data to be latched. The second node is connected to the sense amplifier unit and latches a second voltage having a voltage level that is inverted from that of the first voltage. A high-level of the first voltage latched in the first node is at a voltage level of the second operating voltage at a time the first voltage is supplied from the multiplexer and transitions to a voltage level of the first operating voltage thereafter.

Inventors

Koji Tabata

Assignees

KIOXIA CORPORATION

Dates

Publication Date: 20260512
Application Date: 20240227
Priority Date: 20230323

Claims (20)

1 . A semiconductor memory device comprising: a memory cell array including a plurality of memory cell transistors; and a sense amplifier provided between the memory cell array and an input/output circuit, wherein the sense amplifier includes a data latch circuit configured to operate at a first operating voltage and to latch data to be written to the memory cell transistors and data read from the memory cell transistors, a multiplexer unit configured to operate at a second operating voltage different from the first operating voltage and provided between the input/output circuit and the data latch circuit, a sense amplifier unit configured to latch data read from the memory cell transistors at a time of reading in the data latch circuit and to store the data latched in the data latch circuit in the memory cell transistors at a time of writing, the data latch circuit includes a first node connected to the multiplexer unit and in which a first voltage, which is supplied from the multiplexer unit via a signal line in accordance with data to be latched in the data latch circuit, is latched, and a second node connected to the sense amplifier unit and in which a second voltage having a voltage level that is inverted from that of the first voltage, is latched, and a high-level of the first voltage latched in the first node is at a voltage level of the second operating voltage at a time the first voltage is supplied from the multiplexer unit via the signal line and transitions to a voltage level of the first operating voltage thereafter.
2 . The semiconductor memory device according to claim 1 , wherein the data latch circuit includes a first power supply voltage node to which the first operating voltage is applied, and a first transistor connected to the first power supply voltage node and the first node, the semiconductor memory device further includes a control circuit, and the control circuit sets the first transistor to be in an off state when the first voltage supplied from the multiplexer unit to the first node is latched in the first node, and sets the first transistor to be in an on state after the first voltage is latched in the first node, so that the high-level of the first voltage latched in the first node transitions from the voltage level of the second operating voltage to the voltage level of the first operating voltage.
3 . The semiconductor memory device according to claim 1 , wherein the data latch circuit includes a first power supply voltage node to which the first operating voltage is applied, and a first transistor connected to the first power supply voltage node and the first node, the semiconductor memory device further includes a control circuit, and the control circuit applies a third operating voltage that is at an intermediate voltage level between the voltage level of the first operating voltage and a ground voltage level to a gate of the first transistor when the first voltage supplied from the multiplexer unit to the first node is latched in the first node, and maintains a state in which the third operating voltage is applied to the gate after the first voltage is latched in the first node, so that the high-level of the first voltage latched in the first node transitions from the voltage level of the second operating voltage to the voltage level of the first operating voltage.
4 . The semiconductor memory device according to claim 1 , wherein the multiplexer unit includes a P-channel type transistor and an N-channel type transistor connected in parallel, a transfer gate between the signal line and the data latch circuit, and a ground voltage setting circuit configured to set the signal line to a ground voltage when the semiconductor memory device is powered on.
5 . The semiconductor memory device according to claim 4 , wherein the multiplexer unit includes a second power supply voltage node to which the second operating voltage is applied from a voltage generation circuit, a third power supply voltage node to which the ground voltage is applied, a second transistor provided between the second power supply voltage node and the signal line and configured with one of the N-channel type transistor and the P-channel type transistor, and a third transistor provided between the third power supply voltage node and the signal line and configured with the other of the N-channel type transistor and the P-channel type transistor, and the ground voltage setting circuit is configured to generate a signal capable of turning off the second transistor and turning on the third transistor to gates of the second transistor and the third transistor, so that the voltage of the signal line is set to the ground voltage when the semiconductor memory device is powered on.
6 . The semiconductor memory device according to claim 5 , wherein the ground voltage setting circuit includes: an arithmetic circuit having a first input configured to receive a data signal from the input/output circuit and a second input configured to receive a control signal, and configured to generate the signal capable of turning off the second transistor and turning on the third transistor based on a level of the data signal and a level of the control signal.
7 . The semiconductor memory device according to claim 6 , wherein the arithmetic circuit is a NAND circuit and the control signal is inverted from an input control signal that is generated by a control circuit of the semiconductor memory device.
8 . The semiconductor memory device according to claim 4 , wherein the multiplexer unit includes a second power supply voltage node to which the second operating voltage is applied from the voltage generation circuit, a third power supply voltage node to which the ground voltage is applied, a second transistor provided between the second power supply voltage node and the signal line and configured with one of the N-channel type transistor and the P-channel type transistor, and a third transistor provided between the third power supply voltage node and the signal line and configured with the other of the N-channel type transistor and the P-channel type transistor, the ground voltage setting circuit includes a fourth transistor provided between the second power supply voltage node and the second transistor, and a fifth transistor provided between the third power supply voltage node and the signal line, and the ground voltage setting circuit is controlled to turn off the fourth transistor and turn on the fifth transistor, so that the signal line is set to the ground voltage when the semiconductor memory device is powered on.
9 . The semiconductor memory device according to claim 1 , further comprising: a first chip including the memory cell array and a plurality of first bonding pads; and a second chip including the sense amplifier and a plurality of second bonding pads, wherein the first chip and the second chip are bonded together by bonding the first bonding pads to the second bonding pads.
10 . The semiconductor memory device according to claim 1 , wherein the first operating voltage is higher than the second operating voltage.
11 . A method of operating a semiconductor memory device comprising a memory cell array including a plurality of memory cell transistors and a sense amplifier provided between the memory cell array and an input/output circuit, wherein the sense amplifier includes a data latch circuit configured to operate at a first operating voltage and to latch data to be written to the memory cell transistors and data read from the memory cell transistors, a multiplexer unit configured to operate at a second operating voltage different from the first operating voltage and provided between the input/output circuit and the data latch circuit, a sense amplifier unit configured to latch data read from the memory cell transistors at a time of reading in the data latch circuit and to store the data latched in the data latch circuit in the memory cell transistors at a time of writing, and the method includes latching a first voltage, which is supplied from the multiplexer unit via a signal line in accordance with data to be latched in the data latch circuit, at a first node of the data latch circuit connected to the multiplexer unit; latching a second voltage having a voltage level that is inverted from that of the first voltage in a second node connected to the sense amplifier unit; and transitioning a high-level of the first voltage latched in the first node, which is at a voltage level of the second operating voltage at a time the first voltage is supplied from the multiplexer unit via the signal line, to a voltage level of the first operating voltage thereafter.
12 . The method according to claim 11 , wherein the data latch circuit includes a first power supply voltage node to which the first operating voltage is applied, and a first transistor connected to the first power supply voltage node and the first node, and the method further includes setting the first transistor to be in an off state when the first voltage supplied from the multiplexer unit to the first node is latched in the first node, and setting the first transistor to be in an on state after the first voltage is latched in the first node, so that the high-level of the first voltage latched in the first node transitions from the voltage level of the second operating voltage to the voltage level of the first operating voltage.
13 . The method according to claim 11 , wherein the data latch circuit includes a first power supply voltage node to which the first operating voltage is applied, and a first transistor connected to the first power supply voltage node and the first node, the method further includes applying a third operating voltage that is at an intermediate voltage level between the voltage level of the first operating voltage and a ground voltage level to a gate of the first transistor when the first voltage supplied from the multiplexer unit to the first node is latched in the first node; and maintaining a state in which the third operating voltage is applied to the gate after the first voltage is latched in the first node, so that the high-level of the first voltage latched in the first node transitions from the voltage level of the second operating voltage to the voltage level of the first operating voltage.
14 . The method according to claim 11 , wherein the multiplexer unit includes a P-channel type transistor and an N-channel type transistor connected in parallel, and a transfer gate between the signal line and the data latch circuit, and the method further includes setting the signal line to a ground voltage when the semiconductor memory device is powered on.
15 . The method according to claim 14 , wherein the multiplexer unit includes a second power supply voltage node to which the second operating voltage is applied from a voltage generation circuit, a third power supply voltage node to which the ground voltage is applied, a second transistor provided between the second power supply voltage node and the signal line and configured with one of the N-channel type transistor and the P-channel type transistor, and a third transistor provided between the third power supply voltage node and the signal line and configured with the other of the N-channel type transistor and the P-channel type transistor, and the method further includes generating a signal capable of turning off the second transistor and turning on the third transistor to gates of the second transistor and the third transistor, so that the voltage of the signal line is set to the ground voltage when the semiconductor memory device is powered on.
16 . The method according to claim 15 , wherein the multiplexer unit includes an arithmetic circuit having a first input configured to receive a data signal from the input/output circuit and a second input configured to receive a control signal, and configured to generate the signal capable of turning off the second transistor and turning on the third transistor based on a level of the data signal and a level of the control signal.
17 . The method according to claim 16 , wherein the arithmetic circuit is a NAND circuit and the control signal is inverted from an input control signal that is generated by a control circuit of the semiconductor memory device.
18 . The method according to claim 14 , wherein the multiplexer unit includes a second power supply voltage node to which the second operating voltage is applied from the voltage generation circuit, a third power supply voltage node to which the ground voltage is applied, a second transistor provided between the second power supply voltage node and the signal line and configured with one of the N-channel type transistor and the P-channel type transistor, and a third transistor provided between the third power supply voltage node and the signal line and configured with the other of the N-channel type transistor and the P-channel type transistor, a fourth transistor provided between the second power supply voltage node and the second transistor, and a fifth transistor provided between the third power supply voltage node and the signal line, and the method further includes turning off the fourth transistor and turning on the fifth transistor when the semiconductor memory device is powered on, so that the signal line is set to the ground voltage.
19 . The method according to claim 11 , wherein the semiconductor memory device further comprises: a first chip that includes the memory cell array and a plurality of first bonding pads; and a second chip that includes the sense amplifier and a plurality of second bonding pads, wherein the first chip and the second chip are bonded together by bonding the first bonding pads to the second bonding pads.
20 . The method according to claim 11 , wherein the first operating voltage is higher than the second operating voltage.

Description

CROSS-REFERENCE TO RELATED APPLICATION(S) This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2023-046722, filed Mar. 23, 2023, the entire contents of which are incorporated herein by reference. FIELD Embodiments described herein relate generally to a semiconductor memory device. BACKGROUND A NAND-type flash memory is known as one type of semiconductor memory device. DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a schematic configuration of a memory system of a first embodiment. FIG. 2 is a block diagram showing a schematic configuration of a semiconductor memory device of a first embodiment. FIG. 3 is a timing chart showing an operation example of the semiconductor memory device of the first embodiment at the time of data writing. FIG. 4 is a circuit diagram showing a configuration of the semiconductor memory device of the first embodiment. FIG. 5 is a cross-sectional diagram showing a cross-sectional structure of a semiconductor memory device of the first embodiment. FIG. 6 is a block diagram showing a configuration of a sense amplifier of the first embodiment. FIG. 7 is a block diagram showing a schematic configuration of a sense amplifier unit of the first embodiment. FIG. 8 is a circuit diagram showing a configuration of a data latch circuit of the first embodiment. FIG. 9 is a block diagram showing configurations of a data latch circuit and an input/output circuit of the first embodiment. FIG. 10 is a block diagram showing a configuration of a sense amplifier unit of a first embodiment. FIGS. 11A to 11K are timing charts showing operation examples of the semiconductor memory device of the first embodiment. FIG. 12 is a circuit diagram showing an operation example of a data latch circuit of the first embodiment. FIG. 13 is a circuit diagram showing an operation example of a data latch circuit of the first embodiment. FIGS. 14A to 14K are timing charts showing operation examples of the semiconductor memory device of the first embodiment. FIGS. 15A to 15D are timing charts showing operation examples of the semiconductor memory device of the first embodiment. FIG. 16 is a block diagram showing a configuration of a sense amplifier unit of a second embodiment. FIG. 17 is a cross-sectional diagram showing a cross-sectional structure of a semiconductor memory device of another embodiment. DETAILED DESCRIPTION Embodiments provide a semiconductor memory device capable of reducing power consumption. In general, according to one embodiment, the semiconductor memory device includes a memory cell array including a plurality of memory cell transistors, and a sense amplifier provided between the memory cell array and an input/output circuit. The sense amplifier has a data latch circuit, a multiplexer unit, and a sense amplifier unit. The data latch circuit is configured to operate at a first operating voltage and to latch data written to the memory cell transistor and data read from the memory cell transistor. The multiplexer unit is configured to operate at a second operating voltage different from the first operating voltage and provided between the input/output circuit and the data latch circuit. The sense amplifier unit is configured to latch data read from the memory cell transistors at a time of reading in the data latch circuit and latches the data in the data latch circuit, and to store the data latched in the data latch circuit in the memory cell transistors at a time of writing. The data latch circuit has a first node and a second node. The first node is connected to the multiplexer unit and latches a first voltage supplied from the multiplexer unit via a signal line in accordance with data to be latched in the data latch circuit. The second node is connected to the sense amplifier unit and latches a second voltage having a voltage level that is inverted from that of the first voltage. A high-level of the first voltage latched in the first node is at a voltage level of the second operating voltage at a time the first voltage is supplied from the multiplexer unit via the signal line and transitions to a voltage level of the first operating voltage thereafter Hereinafter, embodiments will be described with reference to drawings. In order to facilitate understanding of the description, the same elements are designated by the same reference numerals as much as possible in each drawing, and description thereof is not repeated. 1. First Embodiment A semiconductor memory device of a first embodiment will be described. A semiconductor memory device according to the present embodiment is a non-volatile memory device configured as a NAND-type flash memory. 1.1 Configuration of Memory System As shown in FIG. 1, the memory system of the present embodiment includes a memory controller 1 and a semiconductor memory device 2. The semiconductor memory device 2 is a non-volatile memory device configured as a NAND-type flash memory. The memory system may be co