US-12626736-B2 - Semiconductor device

US12626736B2US 12626736 B2US12626736 B2US 12626736B2US-12626736-B2

Abstract

A semiconductor device includes a first semiconductor die including a first interface circuit; and a second semiconductor die stacked with the first semiconductor die and including a second interface circuit connected to the first semiconductor die by a plurality of via structures, wherein the first interface circuit is configured to generate an error detection code for transmission data and transmit the data signal including the transmission data and the error detection code to the second interface circuit through at least some of the plurality of via structures, and the second interface circuit is configured to generate response data indicating whether the data signal is normally received and an error correction code of the response data, and transmit a response signal including the response data and the error correction code to the first interface circuit through at least one via structure among the plurality of via structures.

Inventors

Woohyun Son
Jungwoo Jang
Mincheol KWAK
Taehong JANG

Assignees

SAMSUNG ELECTRONICS CO., LTD.

Dates

Publication Date: 20260512
Application Date: 20240621
Priority Date: 20231226

Claims (20)

1 . A semiconductor device comprising: a first semiconductor die including a first interface circuit configured to output a data signal and a transmission clock signal, wherein the first interface circuit includes a cyclic redundancy check (CRC) encoder configured to generate CRC data of transmission data included in the data signal and a buffer memory configured to store the transmission data; a second semiconductor die including a second interface circuit configured to receive the data signal and the transmission clock signal, wherein the second interface circuit includes a CRC decoder configured to decode the CRC data included in the data signal, a response controller configured to generate response data based on the CRC data, the response data indicating completion of transmission of the transmission data or requesting retransmission of the transmission data, and an error correcting code (ECC) encoder configured to generate ECC data of the response data; and a plurality of via structures connecting the first interface circuit to the second interface circuit, wherein the first interface circuit further includes an ECC decoder configured to recover the response data by decoding the ECC data of the response data, and based on the response data, retransmit the transmission data stored in the buffer memory or transmit new transmission data.
2 . The semiconductor device of claim 1 , wherein the first semiconductor die provides a processor, and the second semiconductor die provides a memory.
3 . The semiconductor device of claim 1 , wherein the first semiconductor die includes a first semiconductor substrate, and the second semiconductor die includes a second semiconductor substrate, and wherein each of the plurality of via structures is a through-silicon via that penetrates through at least one of the first semiconductor substrate or the second semiconductor substrate.
4 . The semiconductor device of claim 1 , wherein the first semiconductor die includes a first core circuit connected to the first interface circuit through a first system bus, and wherein the second semiconductor die includes a second core circuit connected to the second interface circuit through a second system bus.
5 . The semiconductor device of claim 1 , wherein the first interface circuit includes a first-in-first-out (FIFO) circuit configured to store the data signal and a plurality of data transmission circuits commonly connected to an output terminal of the FIFO circuit.
6 . The semiconductor device of claim 5 , wherein each of the plurality of data transmission circuits includes a latch and at least one flipflop, each of which being configured to receive the data signal from the FIFO circuit, and a multiplexer configured to connect one of the latch and the at least one flipflop to a corresponding via structure among the plurality of via structures.
7 . The semiconductor device of claim 6 , wherein the latch and the at least one flipflop are synchronized with an internal clock signal, input to the first interface circuit, to store the data signal at a predetermined time, and the multiplexer is configured to sequentially connect the latch and the at least one flipflop to the corresponding via structure.
8 . The semiconductor device of claim 6 , wherein the first interface circuit includes a clock flipflop configured to divide a frequency of an internal clock signal, wherein the transmission clock signal includes a first transmission clock signal having a same frequency as a frequency of the internal clock signal, and a second transmission clock signal output from the clock flipflop, and wherein the multiplexer is configured to receive the first transmission clock signal and the second transmission clock signal.
9 . The semiconductor device of claim 5 , wherein the plurality of via structures include a plurality of data via structures that provide a transmission path for the data signal, and a number of the plurality of data via structures is equal to a number of the plurality of data transmission circuits.
10 . The semiconductor device of claim 1 , wherein the second interface circuit includes a plurality of data reception circuits, each being configured to receive the data signal from the first interface circuit and receive the transmission clock signal from the first interface circuit through at least one clock via structure among the plurality of via structures, and wherein each of the plurality of data reception circuits includes a first flipflop and a second flipflop, connected to a corresponding via structure among the plurality of via structures, and a third flipflop connected to the first flipflop.
11 . The semiconductor device of claim 10 , wherein the first flipflop is configured to store the data signal in response to a rising edge of the transmission clock signal, and the second flipflop and the third flipflop are configured to store the data signal in response to a falling edge of the transmission clock signal.
12 . The semiconductor device of claim 11 , wherein the second interface circuit includes an inverter configured to invert the transmission clock signal and transmit the inverted transmission clock signal to the second flipflop and the third flipflop.
13 . The semiconductor device of claim 11 , wherein the second interface circuit is connected to a clock via structure, among the plurality of via structures, through which the transmission clock signal is transmitted, and includes a delay circuit configured to adjust a phase of the transmission clock signal.
14 . The semiconductor device of claim 1 , wherein the first interface circuit is configured to, based on the response data indicating the completion of transmission of the transmission data, delete the transmission data stored in the buffer memory.
15 . The semiconductor device of claim 1 , wherein the first interface circuit is configured to, based on the response data requesting the retransmission of the transmission data, re-transmit the data signal including the transmission data stored in the buffer memory to the second interface circuit.
16 . A semiconductor device comprising: a first semiconductor die including a first interface circuit; and a second semiconductor die stacked with the first semiconductor die and including a second interface circuit, the second interface circuit being connected to the first semiconductor die by a plurality of via structures, wherein the first interface circuit is configured to generate an error detection code for transmission data and transmit a data signal including the transmission data and the error detection code to the second interface circuit through at least some of the plurality of via structures, and wherein the second interface circuit is configured to generate response data, indicating whether the data signal is normally received, and an error correction code of the response data, and transmit a response signal including the response data and the error correction code to the first interface circuit through at least one via structure among the plurality of via structures.
17 . The semiconductor device of claim 16 , wherein, based on an error being detected from the transmission data included in the data signal based on the error detection code, the second interface circuit is configured to generate the response data requesting retransmission of the transmission data.
18 . The semiconductor device of claim 17 , wherein the first interface circuit is configured to correct an error in the response data by using the error correction code, and determine whether to retransmit the transmission data based on the response data of which error has been corrected.
19 . The semiconductor device of claim 16 , wherein the at least some of the plurality of via structures through which the data signal and the error detection code are transmitted is different from the at least one via structure through which the response signal is transmitted.
20 . A semiconductor device comprising: a first semiconductor die including a first interface circuit; and a second semiconductor die including a second interface circuit connected to the first interface circuit by a plurality of via structures, the second semiconductor die being stacked with the first semiconductor die, wherein the first interface circuit includes a plurality of data transmission circuits connected to data via structures among the plurality of via structures and a first-in-first-out (FIFO) circuit commonly connected to the plurality of data transmission circuits, and wherein each of the plurality of data transmission circuits includes a latch and at least one flipflop, each being configured to receive transmission data output from the FIFO circuit, and a multiplexer connected between the latch and the at least one flipflop and a corresponding data via structure among the data via structures.

Description

CROSS-REFERENCE TO RELATED APPLICATION(S) This application claims benefit of priority to Korean Patent Application No. 10-2023-0190870 filed on Dec. 26, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. BACKGROUND One or more example embodiments of the disclosure relate to a semiconductor device. Semiconductor devices may include various circuits to perform operations. In order to improve the performance of semiconductor devices and reduce power consumption, three-dimensional (3D) semiconductor devices in which circuits are distributed across a plurality of semiconductor dies and the plurality of semiconductor dies are stacked have been proposed. In a 3D semiconductor device, at least some of the circuits included in different semiconductor dies may be connected to each other through via structures to exchange data signals, clock signals, and the like. Therefore, in order to improve the reliability and integration of 3D semiconductor devices, it is needed to improve a data transfer rate through via structures and appropriately limit a number of via structures. SUMMARY One or more example embodiments of the disclosure provide a semiconductor device having improved reliability of communication between semiconductor dies connected by via structures and stacked on each other. According to an aspect of an example embodiment of the disclosure, a semiconductor device may include: a first semiconductor die including a first interface circuit configured to output a data signal and a transmission clock signal, wherein the first interface circuit includes a cyclic redundancy check (CRC) encoder configured to generate CRC data of transmission data included in the data signal and a buffer memory configured to store the transmission data, a second semiconductor die including a second interface circuit configured to receive the data signal and the transmission clock signal, wherein the second interface circuit includes a CRC decoder configured to decode the CRC data included in the data signal, a response controller configured to generate response data based on the CRC data, the response data indicating completion of transmission of the transmission data or requesting retransmission of the transmission data, and an error correcting code (ECC) encoder configured to generate ECC data of the response data; and a plurality of via structures connecting the first interface circuit to the second interface circuit, wherein the first interface circuit further includes an ECC decoder configured to recover the response data by decoding the ECC data of the response data, and based on the response data, retransmit the transmission data stored in the buffer memory or transmit new transmission data. According to an aspect of an example embodiment of the disclosure, a semiconductor device may include: a first semiconductor die including a first interface circuit; and a second semiconductor die stacked with the first semiconductor die and including a second interface circuit, the second interface circuit being connected to the first semiconductor die by a plurality of via structures, wherein the first interface circuit is configured to generate an error detection code for transmission data and transmit a data signal including the transmission data and the error detection code to the second interface circuit through at least some of the plurality of via structures, and wherein the second interface circuit is configured to generate response data, indicating whether the data signal is normally received, and an error correction code of the response data, and transmit a response signal including the response data and the error correction code to the first interface circuit through at least one via structure among the plurality of via structures. According to an aspect of an example embodiment of the disclosure, a semiconductor device may include: a first semiconductor die including a first interface circuit; and a second semiconductor die including a second interface circuit connected to the first interface circuit by a plurality of via structures, the second semiconductor die being stacked with the first semiconductor die, wherein the first interface circuit includes a plurality of data transmission circuits connected to data via structures among the plurality of via structures and a first-in-first-out (FIFO) circuit commonly connected to the plurality of data transmission circuits, and wherein each of the plurality of data transmission circuits includes a latch and at least one flipflop, each being configured to receive transmission data output from the FIFO circuit, and a multiplexer connected between the latch and the at least one flipflop and a corresponding data via structure among the data via structures. BRIEF DESCRIPTION OF DRAWINGS The above and other aspects, features, and advantages of certain example embodiments of the disclosure will be more clearly under