US-12626737-B2 - Temperature based block read

Abstract

A solid-state memory device that performs temperature-based block reads includes an array of non-volatile memory cells and a controller. The controller is configured to track a temperature for a region of the array of non-volatile memory cells in response to data being written to the region. The controller is configured to determine a read voltage threshold for a read request for the region based on both the tracked temperature for the region and a temperature determined for the region in response to a read request. The controller is configured to perform a read operation for the region using the determined read voltage threshold.

Inventors

• MANOJ M. SHENOY
• Arunkumar Mani
• ARVIND SUNDARAMOORTHI

Assignees

• SanDisk Technologies, Inc.

Dates

Publication Date

20260512

Application Date

20230811

Claims (20)

1. 1 . An apparatus, comprising: an array of non-volatile memory cells; and a controller configured to: track a temperature for a region of the array of non-volatile memory cells in response to data being written to the region; determine a read voltage threshold shift for a read request for the region based, at least in part, on: the tracked temperature for the region; and a determined temperature of the region at a time at which the read request is received, the read voltage threshold shift being stored in a two-dimensional data structure indexed by: the tracked temperature for the region; and the determined temperature of the region; and perform a read operation for the region using the determined read voltage threshold shift.
2. 2 . The apparatus of claim 1 , wherein the data structure is stored in a configuration file for the controller.
3. 3 . The apparatus of claim 1 , wherein the read voltage threshold shift comprises an offset from a default read voltage threshold value.
4. 4 . The apparatus of claim 1 , wherein the tracked temperature for the region is stored in an address mapping structure for the region.
5. 5 . The apparatus of claim 4 , wherein the address mapping structure comprises an inverted global address table mapping physical addresses of the array of non-volatile memory cells to logical addresses.
6. 6 . The apparatus of claim 4 , wherein the address mapping structure is cached in volatile memory for the controller.
7. 7 . The apparatus of claim 4 , wherein the tracked temperature for the region is stored in the address mapping structure without any other temperatures for the same region.
8. 8 . The apparatus of claim 7 , wherein the tracked temperature for the region is stored in the address mapping structure without any time indicator associated with the tracked temperature.
9. 9 . The apparatus of claim 1 , wherein the region comprises an erase block of the array of non-volatile memory cells.
10. 10 . A method, comprising: recording write temperatures per block of a non-volatile memory as data is programmed to the non-volatile memory; determining a read voltage threshold shift for a read request based, at least in part, on: the recorded write temperatures; and a temperature for a region of the non-volatile memory at which data associated with the read request is stored, the temperature for the region being determined in response to receiving the read request, wherein the read voltage threshold shift is stored in a two-dimensional data structure indexed by: the recorded write temperatures; and the temperature of the region determined in response to receiving the read request; and reading data from the region of the non-volatile memory using the read voltage threshold shift.
11. 11 . The method of claim 10 , wherein the read voltage threshold shift comprises an offset from a default read voltage threshold value.
12. 12 . The method of claim 10 , wherein the recorded write temperatures are stored in an address mapping structure for the non-volatile memory.
13. 13 . The method of claim 12 , wherein the address mapping structure comprises an inverted global address table mapping physical addresses of the non-volatile memory to logical addresses.
14. 14 . The method of claim 12 , wherein the recorded write temperatures stored in the address mapping structure comprise a single write temperature per block of the non-volatile memory.
15. 15 . The method of claim 14 , wherein the recorded write temperatures are stored in the address mapping structure without any time indicators associated with the recorded write temperatures.
16. 16 . An apparatus comprising: means for sensing write temperatures for a non-volatile memory; means for sensing a read temperature for the non-volatile memory in response to a read request; means for determining a read voltage threshold for the read request based on both the sensed write temperatures and the sensed read temperature; and means for reading data from the non-volatile memory using the determined read voltage threshold.
17. 17 . The apparatus of claim 16 , further comprising means for storing the sensed write temperatures in an inverted global address table without any time indicators associated with the sensed write temperatures, the sensed write temperatures comprising a single write temperature stored in the inverted global address table per block of the non-volatile memory.
18. 18 . The apparatus of claim 16 , wherein the means for determining the read voltage threshold comprises a two-dimensional data structure indexed by the sensed write temperatures and the sensed read temperature.
19. 19 . The apparatus of claim 16 , further comprising means for caching the sensed write temperatures in volatile memory to facilitate access during one or more operations.
20. 20 . The apparatus of claim 16 , wherein the means for storing the sensed write temperatures comprises a configuration file that includes a single write temperature per block of the non-volatile memory.

Description

CROSS-REFERENCES TO RELATED APPLICATIONS This application claims the benefit of U.S. Provisional Patent Application No. 63/440,839 entitled “TEMPERATURE BASED BLOCK READ” and filed on Jan. 24, 2023, for Manoj M. Shenoy et al., which is incorporated herein by reference. TECHNICAL FIELD The present disclosure, in various embodiments, relates to storage and/or memory devices and more particularly relates to temperature based block reads for storage and/or memory devices. BACKGROUND Memory devices may be organized into erase blocks or other regions of memory elements. Erase blocks may further be organized into pages, which are the smallest programmable unit physically made up of a row of cells linked on the same word line, or the like. A fixed read voltage threshold or a fixed read voltage threshold shift from a baseline read voltage threshold may be used for all blocks; however, optimal read voltage thresholds may vary due to different conditions at read time and/or write time, and read retry processes that occur in response to data errors can be time consuming, drastically reducing performance. SUMMARY Various embodiments are disclosed, including apparatuses, systems, and methods for temperature based block reads. In some embodiments, an apparatus includes an array of non-volatile memory cells and/or a controller. The controller, in one embodiment, is configured to track a temperature for a region of the array of non-volatile memory cells in response to data being written to the region. In certain embodiments, the controller is configured to determine a read voltage threshold for a read request for the region based on both a tracked temperature for the region and a temperature determined for the region in response to the read request. The controller, in a further embodiment, is configured to perform a read operation for the region using the determined read voltage threshold. A method, in one embodiment, includes recording write temperatures per block of a non-volatile memory as data is programmed to the non-volatile memory. In some embodiments, the method includes looking up a read voltage threshold shift for a read request based on both a recorded write temperature and a temperature determined in response to the read request. The method, in a further embodiment, includes reading data from the non-volatile memory using the read voltage threshold shift to satisfy the read request. An apparatus, in one embodiment, includes means for sensing write temperatures for a non-volatile memory. The apparatus, in certain embodiments, includes means for sensing a read temperature for the non-volatile memory in response to a read request. The apparatus, in some embodiments, includes means for determining a read voltage threshold for the read request based on both a sensed write temperature and a sensed read temperature. The apparatus, in a further embodiment, includes means for reading data from the non-volatile memory using the determined read voltage threshold. BRIEF DESCRIPTION OF THE DRAWINGS A more particular description is included below with reference to specific embodiments illustrated in the appended drawings. Understanding that these drawings depict only certain embodiments of the disclosure and are not therefore to be considered to be limiting of its scope, the disclosure is described and explained with additional specificity and detail through the use of the accompanying drawings, in which: FIG. 1A is a schematic block diagram illustrating one embodiment of a system for temperature based block reads; FIG. 1B is a schematic block diagram illustrating another embodiment of a system for temperature based block reads; FIG. 2 is a schematic block diagram illustrating one embodiment of a string of memory cells; FIG. 3A is a schematic block diagram illustrating one embodiment of an array of memory cells; FIG. 3B is a diagram of the voltage shift across an array of memory cells; FIG. 4 is a schematic block diagram illustrating one embodiment of a three-dimensional (3D), vertical NAND flash memory structure; FIG. 5 is a schematic block diagram illustrating one embodiment of a voltage determination component for temperature based block reads; FIG. 6 is a schematic block diagram illustrating one embodiment of a reference table; FIG. 7 is a schematic flow chart diagram illustrating one embodiment of a method for temperature based block reads; FIG. 8 is a schematic flow chart diagram illustrating another embodiment of a method for temperature based block reads; and FIG. 9 is a schematic flow chart diagram illustrating a further embodiment of a method for temperature based block reads. DETAILED DESCRIPTION Aspects of the present disclosure may be embodied as an apparatus, system, method, or computer program product. Accordingly, aspects of the present disclosure may take the form of an entirely software embodiment (including firmware, resident software, micro-code, or the like) or an embodiment combining software and hardwar