US-12626738-B2 - Semiconductor memory device including memory string and plurality of select transitstors and method including a write operation

US12626738B2US 12626738 B2US12626738 B2US 12626738B2US-12626738-B2

Abstract

In a semiconductor memory device, in a write operation performed to a memory cell transistor, a first voltage is applied to a first word line and a second voltage lower than the first voltage is applied to a second word line. When a stop command is received during the write operation, a third voltage lower than the second voltage is applied to the first and second word lines, thereafter a fourth voltage higher than the third voltage is applied to a first selection line, thereon or thereafter a fifth voltage higher than the fourth voltage is applied to the first and second word lines, thereafter a sixth voltage lower than the fourth voltage is applied to the first selection line, and thereafter a seventh voltage is applied to the first and second word lines.

Inventors

Hiroki Date

Assignees

KIOXIA CORPORATION

Dates

Publication Date: 20260512
Application Date: 20240618
Priority Date: 20180906

Claims (12)

1 . A semiconductor memory device comprising: a bit line extending in a first direction; a source line a memory cell array including a memory string including a plurality of memory cell transistors connected in series, the memory cell transistors including a first memory cell transistor and a second memory cell transistor, a first selection transistor connected between the bit line and the memory string, and a second selection transistor connected between the memory string and the source line; a plurality of word lines each extending in the second direction crossing the first direction, and being arranged in a third direction crossing the first direction and the second direction, the word lines being connected to gate electrodes of the memory cell transistors, respectively, the word lines including a first word line connected to the gate electrode of the first memory cell transistor, and a second word line connected to the gate electrode of the second memory cell transistor a first selection line connected to a gate electrode of the first selection transistor; and a second selection line connected to a gate electrode of the second selection transistor, wherein in a program operation performed to the first memory cell transistor, at a first timing a first voltage is applied to the first word line, a second voltage lower than the first voltage is applied to the second word line, a third voltage lower than the first voltage is applied to the first selection line, and a fourth voltage lower than the seventh voltage is applied to the second selection line, at a second timing after the first timing, a fifth voltage lower than the first voltage is applied to the first word line, a sixth voltage lower than the first voltage is applied to the second word line, a seventh voltage higher than the third voltage is applied to the first selection line, and an eighth voltage higher than the fourth voltage is applied to the second selection line, at a third timing after the second timing, a ninth voltage lower than the first voltage is applied to the first word line, a tenth voltage lower than the first voltage is applied to the second word line, an eleventh voltage lower than the seventh voltage is applied to the first selection line, and a twelfth voltage lower than the eighth voltage is applied to the second selection line, and at a fourth timing after the third timing, a thirteenth voltage lower than the ninth voltage is applied to the first word line, a fourteenth voltage lower than the tenth voltage is applied to the second word line, a fifteenth voltage lower than the seventh voltage is applied to the first selection line, and a sixteenth voltage lower than the eighth voltage is applied to the second selection line.
2 . The semiconductor memory device according to claim 1 , wherein when a command to stop is received during the program operation, voltages applied to the first selection line and the second selection line are decreased, and thereafter voltages applied to the first word line and the second word line are decreased.
3 . The semiconductor memory device according to claim 2 , wherein when the command to stop is received during the program operation, in the program operation, at a fifth timing between the first timing and the second timing, a seventeenth voltage lower than the second voltage is applied to the first word line and to the second word line.
4 . The semiconductor memory device according to claim 3 , wherein after the fourth timing of the program operation, the first word line and the second word line are brought into a floating state.
5 . The semiconductor memory device according to claim 4 , wherein after the first word line and the second word line are brought into the floating state, voltages of the first word line and the second word line rise.
6 . The semiconductor memory device according to claim 2 , wherein at the fifth timing of the program operation, an amount of decrease of the voltage of the first word line falling to the seventeenth voltage and an amount of increase of the voltage of the first word line rising to the fifth voltage are smaller than an amount of increase of the voltage of the first word line rising to the first voltage and an amount of decrease of the voltage of the first word line falling to the thirteenth voltage.
7 . The semiconductor memory device according to claim 1 , further comprising: a first to fourth voltage supply lines; a voltage driver configured to supply voltages to the first to fourth voltage supply lines: a first transistor connected between the first voltage supply line and the first word line, a second transistor connected between the second voltage supply line and the second word line, a third transistor connected between the third voltage supply line and the first selection line; and a fourth transistor connected between the fourth voltage supply line and the second selection line.
8 . The semiconductor memory device according to claim 7 , wherein after the fourth timing of the program operation, the first word line and the second word line are brought into a floating state, and voltage of the first word line and the second word line rise while the first and second voltage supply lines are disconnected from the first and second word lines and the third and fourth voltage supply lines are disconnected from the first and second selection lines.
9 . The semiconductor memory device according to claim 7 , further comprising: a block decoder configured to apply an eighteenth voltage higher than the fifth voltage at least during the write operation.
10 . The semiconductor memory device according to claim 1 , wherein the program operation is started in response to a write command.
11 . The semiconductor memory device according to claim 2 , wherein a write operation including the program operation and a verify operation is performed, and when the command to stop is received during the program operation, the voltages applied to the first selection line and the second selection line are decreased, and thereafter the voltages applied to the first word line and the second word line are decreased.
12 . A method for controlling a semiconductor memory device, the semiconductor memory device including: a bit line extending in a first direction; a source line; a memory cell array including a memory string including a plurality of memory cell transistors connected in series, the memory cell transistors including a first memory cell transistor and a second memory cell transistor, a first selection transistor connected between the bit line and the memory string, and a second selection transistor connected between the memory string and the source line; a plurality of word lines each extending in the second direction crossing the first direction, and being arranged in a third direction crossing the first direction and the second direction, the word lines being connected to gate electrodes of the memory cell transistors, respectively, the word lines including a first word line connected to the gate electrode of the first memory cell transistor, and a second word line connected to the gate electrode of the second memory cell transistor; a first selection line connected to a gate electrode of the first selection transistor; and a second selection line connected to a gate electrode of the second selection transistor, the method including performing a program operation to the first memory cell transistor, wherein at a first timing of the program operation, a first voltage is applied to the first word line, a second voltage lower than the first voltage is applied to the second word line, a third voltage lower than the first voltage is applied to the first selection line, and a fourth voltage lower than the seventh voltage is applied to the second selection line, at a second timing after the first timing of the program operation, a fifth voltage lower than the first voltage is applied to the first word line, a sixth voltage lower than the first voltage is applied to the second word line, a seventh voltage higher than the third voltage is applied to the first selection line, and an eighth voltage higher than the fourth voltage is applied to the second selection line, at a third timing after the second timing of the program operation, a ninth voltage lower than the first voltage is applied to the first word line, a tenth voltage lower than the first voltage is applied to the second word line, an eleventh voltage lower than the seventh voltage is applied to the first selection line, and a twelfth voltage lower than the eighth voltage is applied to the second selection line, and at a fourth timing after the third timing of the program operation, a thirteenth voltage lower than the ninth voltage is applied to the first word line, a fourteenth voltage lower than the tenth voltage is applied to the second word line, a fifteenth voltage lower than the seventh voltage is applied to the first selection line, and a sixteenth voltage lower than the eighth voltage is applied to the second selection line.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application is a Continuation Application of U.S. application Ser. No. 17/729,114, filed Apr. 26, 2022, which is a U.S. application Ser. No. 16/862,893, filed Apr. 30, 2020, and issued as U.S. Pat. No. 11,335,388 on May 17, 2022, which is a Continuation application of U.S. application Ser. No. 16/259,259, filed on Jan. 28, 2019, and issued as U.S. Pat. No. 10,685,689 on Jun. 16, 2020, which is based upon and claims the benefit of Japanese Patent Application No. 2018-166583, filed on Sep. 6, 2018, the entire contents all of which are incorporated herein by reference. BACKGROUND Field Embodiments according to the present invention relate to a semiconductor memory device. Description of the Related Art A semiconductor memory device including a substrate, a plurality of wirings and a semiconductor film facing the plurality of wirings is well known. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 shows an equivalent circuit diagram showing a schematic configuration of a semiconductor memory device according to a first embodiment; FIG. 2 shows a schematic perspective view of the semiconductor memory device; FIG. 3 shows a schematic enlarged view of FIG. 2; FIG. 4 shows a schematic histogram showing distribution of a threshold voltage of a memory cell MC; FIG. 5 shows a schematic waveform diagram showing a read operation according to the first embodiment; FIG. 6 shows a schematic waveform diagram showing a write operation according to the first embodiment; FIG. 7 shows a schematic waveform diagram showing a write operation according to a first comparative example; FIG. 8 shows a schematic waveform diagram showing a write operation according to a second comparative example; FIG. 9 shows a schematic waveform diagram showing a write operation according to a second embodiment; FIG. 10 shows a schematic waveform diagram showing a write operation according to a third embodiment; and FIG. 11 shows a schematic flow chart for explaining about processing according to a fourth embodiment. DETAILED DESCRIPTION A semiconductor memory device according to one embodiment includes: a substrate; a first memory transistor and a first selection transistor aligned in a first direction intersecting a surface of the substrate and connected to each other; a first wiring connected to a gate electrode of the first memory transistor; and a second wiring connected to a gate electrode of the first selection transistor. Moreover, in a write operation performed to the first memory transistor, at a first timing, a voltage of the first wiring rises, at a second timing after the first timing, the voltage of the first wiring falls, at a third timing after the second timing, a voltage of the second wiring rises, at the third timing or at a fourth timing after the third timing, the voltage of the first wiring rises, at a fifth timing after the voltage of the first wiring rises at the third timing or the fourth timing, the voltage of the second wiring falls, and at a sixth timing after the fifth timing, the voltage of the first wiring falls. A semiconductor memory device according to one embodiment includes: a substrate; a first memory transistor and a first selection transistor aligned in a first direction intersecting a surface of the substrate and connected to each other; a first wiring connected to a gate electrode of the first memory transistor; and a second wiring connected to a gate electrode of the first selection transistor. Moreover, in a write operation performed to the first memory transistor, at a first timing, a voltage of the first wiring rises, at a second timing after the first timing, a voltage of the second wiring rises, at a third timing after the second timing, the voltage of the second wiring further rises, at a fourth timing after the third timing, the voltage of the second wiring falls, and at a fifth timing after the fourth timing, the voltage of the first wiring falls. A semiconductor memory device according to one embodiment includes: a substrate; a first memory transistor and a first selection transistor aligned in a first direction intersecting a surface of the substrate and connected to each other; a first wiring connected to a gate electrode of the first memory transistor; a second wiring connected to a gate electrode of the first selection transistor; and a third wiring connected a drain electrode of the first selection transistor. Moreover, in a write operation performed to the first memory transistor, at a first timing, a voltage of the first wiring rises, at a second timing after the first timing, a voltage of the third wiring rises, at a third timing after the second timing, a voltage of the second wiring rises, at a fourth timing after the third timing, the voltage of the third wiring falls, at a fifth timing after the fourth timing, the voltage of the second wiring falls, and at a sixth timing after the fifth timing, the voltage of the first wiring falls. Next, semiconductor m