US-12626739-B1 - Pointer information encoded in weighted increment signals

Abstract

An example non-transitory computer readable medium includes stored instructions which, when executed by a processor, cause the processor to convert an input clockwide pulse received from an upstream circuit running in a first clock domain into an output clockwide pulse that is synchronized to a second clock domain. The instructions further cause the processor to advance a count in response to the output clockwide pulse that is synchronized to the second clock domain.

Inventors

• Alan Stewart Geist

Assignees

• SYNOPSYS, INC.

Dates

Publication Date

20260512

Application Date

20240620

Claims (20)

1. 1 . A non-transitory computer readable medium comprising stored instructions, which when executed by a processor, cause the processor to: receive an electronic signal including a first plurality of clockwide pulses in a first clock domain that runs at a first clock frequency; convert a first portion of the electronic signal to a first clockwide pulse in a second clock domain that runs at a second clock frequency, using a first pulse-to-pulse synchronizer circuit of a bank of pulse-to-pulse synchronizer circuits, wherein the first pulse-to-pulse synchronizer circuit weights the first clockwide pulse by a first value, and wherein the first value is greater than one; and advance a count of a pointer counter in response to the first clockwide pulse, where the count is advanced by a number that is at least equal to the first value.
2. 2 . The non-transitory computer readable medium of claim 1 , wherein the first clock frequency is higher than the second clock frequency.
3. 3 . The non-transitory computer readable medium of claim 1 , wherein the second clock frequency is higher than the first clock frequency.
4. 4 . The non-transitory computer readable medium of claim 1 , wherein the first clock frequency is equal to the second clock frequency, but a phase relationship between the first clock domain and the second clock domain is different.
5. 5 . The non-transitory computer readable medium of claim 1 , wherein the stored instructions further cause the processor to: convert a second portion of the electronic signal to a second clockwide pulse in the second clock domain, using a second pulse-to-pulse synchronizer circuit of the bank of pulse-to-pulse synchronizer circuits, wherein the second pulse-to-pulse synchronizer circuit weights the second clockwide pulse by a second value.
6. 6 . The non-transitory computer readable medium of claim 5 , wherein the count is advanced by a number that is equal to a sum of the first value and the second value.
7. 7 . The non-transitory computer readable medium of claim 5 , wherein the second value is different from the first value.
8. 8 . The non-transitory computer readable medium of claim 1 , wherein the processor comprises a component of a synchronizing first in, first out buffer, and the count indicates a pointer pointing to a location in the synchronizing first in, first out buffer at which a data word is stored.
9. 9 . The non-transitory computer readable medium of claim 8 , wherein the synchronizing first in, first out buffer receives a plurality of input words of data in a single input clock period.
10. 10 . The non-transitory computer readable medium of claim 8 , wherein the synchronizing first in, first out buffer provides a plurality of output words of data to a downstream circuit in a single output clock period.
11. 11 . A synchronizing first-in-first-out buffer, comprising: an input port that receives a plurality of input words of data from a plurality of input ports and selects a storage element of a plurality of storage elements to which to provide each input word of data of the plurality of input words of data, wherein the plurality of input words of data are in a first clock domain; a pointer generation and synchronization circuit having an input to receive an input clockwide pulse generated in the first clock domain, the pointer generation and synchronization circuit comprising: a first pulse-to-pulse synchronizer circuit to convert at least a portion of the input clockwide pulse into an output clockwide pulse that is synchronized to a second clock domain, wherein the first pulse-to-pulse synchronizer circuit is configured to weight at least a portion of the output clockwide pulse by a first value that is greater than one; a first pointer counter having an input coupled to an output of the first pulse-to-pulse synchronizing circuit, to advance a count in response to receiving the output clockwide pulse that is synchronized to the second clock domain by a value that is at least equal to the first value; and a second pointer counter to receive a pointer generated in the second clock domain; and an output port to receive the plurality of input words of data from the plurality of storage elements and to receive the pointer generated in the second clock domain and to generate an output word of data selected from among the plurality of input words of data based on the pointer generated in the second clock domain.
12. 12 . The synchronizing first-in-first-out buffer of claim 11 , wherein the pointer generation and synchronization circuit further comprises: a second pulse-to-pulse synchronizer circuit to convert another portion of the input clockwide pulse into another output clockwide pulse that is synchronized to the second clock domain, wherein the second pulse-to-pulse synchronizer circuit is configured to weight at least a portion of the output clockwide pulse by a second value.
13. 13 . The synchronizing first-in-first-out buffer of claim 12 , wherein the second pointer counter is configured to advance a count by a number that is equal to a sum of the first value and the second value.
14. 14 . The synchronizing first-in-first-out buffer of claim 12 , wherein the second value is different from the first value.
15. 15 . A method, comprising: receiving an electronic signal including a first plurality of clockwide pulses in a first clock domain that runs at a first clock frequency; converting a first portion of the electronic signal to a first clockwide pulse in a second clock domain that runs at a second clock frequency, using a first pulse-to-pulse synchronizer circuit of a bank of pulse-to-pulse synchronizer circuits, wherein the first pulse-to-pulse synchronizer circuit weights the first clockwide pulse by a first value, and wherein the first value is greater than one; converting a second portion of the electronic signal to a second clockwide pulse in the second clock domain, using a second pulse-to-pulse synchronizer circuit of the bank of pulse-to-pulse synchronizer circuits, wherein the second pulse-to-pulse synchronizer circuit weights the second clockwide pulse by a second value that is equal to one; advancing a count of a pointer counter in response to the first clockwide pulse, where the count is advanced by a number that is equal to a sum of the first value and the second value; and outputting a pointer associated with the electronic signal based on the count.
16. 16 . The method of claim 15 , wherein the first clock frequency is higher than the second clock frequency.
17. 17 . The method of claim 15 , wherein the second clock frequency is higher than the first clock frequency.
18. 18 . The method of claim 15 , wherein the first clock frequency is equal to the second clock frequency, but a phase relationship between the first clock domain and the second clock domain is different.
19. 19 . The method of claim 15 , wherein the bank of pulse-to-pulse synchronizer circuits comprises a component of a synchronizing first in, first out buffer, and the count indicates a pointer pointing to a location in the synchronizing first in, first out buffer at which a data word is stored.
20. 20 . The method of claim 19 , wherein the synchronizing first in, first out buffer receives a plurality of input words of data in a single input clock period.

Description

RELATED APPLICATION This application is a continuation-in-part of U.S. patent application Ser. No. 18/510,037, filed Nov. 15, 2023, which is herein incorporated by reference in its entirety. TECHNICAL FIELD The present disclosure generally relates to integrated circuits, and relates more particularly to communicating pointer information across clock domains by encoding the pointer information in weighted increment signals. BACKGROUND Synchronizing first-in-first-out circuits (also referred to as synchronizing FIFOs) are commonly used in digital logic designs that have multiple clock domains, particularly when those multiple clock domains are asynchronous (i.e., operating at different clock frequencies). For instance, a synchronizing FIFO can be used to synchronize data from a first clock domain into a different, second clock domain. BRIEF DESCRIPTION OF THE DRAWINGS The disclosure will be understood more fully from the detailed description given below and from the accompanying figures of embodiments of the disclosure. The figures are used to provide knowledge and understanding of embodiments of the disclosure and do not limit the scope of the disclosure to these specific embodiments. Furthermore, the figures are not necessarily drawn to scale. FIG. 1 illustrates an example circuit for synchronizing pointer increment signals of the present disclosure; FIG. 2 illustrates an example pointer generation and synchronization circuit employing the circuit of FIG. 1; FIG. 3 illustrates an example synchronizing first-in-first-out buffer employing the pointer generation and synchronization circuit of FIG. 2; FIG. 4 illustrates an example method for conveying pointer information from a first clock domain to a different, second clock domain via an increment signal, according to the present disclosure; FIG. 5 illustrates an example pulse-to-pulse synchronizer circuit that may be used to generate weighted increment signals, according to the present disclosure; FIG. 6 illustrates an example method for conveying pointer information from a first clock domain to a different, second clock domain via a weighted increment signal, according to the present disclosure; and FIG. 7 illustrates a diagram of an example computer system in which embodiments of the present disclosure may operate. DETAILED DESCRIPTION Aspects of the present disclosure relate to communicating pointer information across clock domains by encoding the pointer information in increment or decrement signals. As discussed above, a synchronizing FIFO can be used to synchronize digital information from a first clock domain into a different, second clock domain. Internally, a synchronizing FIFO may use multi-bit gray-coded pointers, which can be passed from one clock domain to another through metastable filters even while changing. However, when gray-coded pointers are incremented, no more than a single bit can be changed with respect to the clock edge on read and write from the synchronizing FIFO. Thus, synchronizing FIFOs that utilize gray-coded pointers can support no more than a single read port and a single write port. Instead of passing actual pointers such as gray-coded pointers from a first clock domain to a second clock domain, examples of the present disclosure may pass increment signals which, upon receipt in the second clock domain, can be used to instruct a pointer counter in the second clock domain to advance its count by an amount that is equal to the number of increment signals that are passed and asserted. Any number of increment signals may be passed. Examples of the present disclosure are particularly useful in synchronizing FIFOs. The use of increment signals rather than gray-coded pointers allows a synchronizing FIFO to support more than one data input (write) port and/or more than one data output (read) port (and, thus to accept more than one input data word and/or to provide more than one output data word). Technical advantages of the present disclosure therefore include, but are not limited to, the ability to support more than one data input (write) port and/or more than one data output (read) port in a synchronizing FIFO that passes data from a first clock domain to a different, second clock domain. This allows the synchronizing FIFO to write more than one data word input and/or read more than one data word output simultaneously (e.g., in a single clock period). Further examples of the present disclosure could be extended to add flexibility to other applications that involve the synchronization of monotonically incrementing or decrementing pointers (or other values) across multiple clock domains. FIG. 1 illustrates an example circuit 100 for synchronizing pointer increment signals (also referred to herein as a synchronizing circuit) of the present disclosure. The circuit 100 illustrated in FIG. 1 is configured as a write-side synchronizing circuit. That is, the circuit 100 is configured to synchronize a pointer increment signal from a write c