US-12626740-B2 - Signal receiver with skew-tolerant strobe gating

Abstract

A first-in-first-out (FIFO) storage structure within an integrated-circuit component is loaded with qualification values corresponding to respective pairs of edges expected within a timing strobe signal transmitted to the integrated-circuit component. The qualification values are sequentially output from the FIFO storage structure during respective cycles of the timing strobe signal and a gate signal is either asserted or deasserted during the respective cycles of the timing strobe signal according to the qualification values output from the FIFO storage structure.

Inventors

• Andrew M. Fuller
• Robert E. Palmer
• Thomas J. Giovannini
• Michael D. Bucher
• Thoai Thai Le

Assignees

• RAMBUS INC.

Dates

Publication Date

20260512

Application Date

20240710

Claims (20)

1. 1 . An integrated circuit component comprising: clock distribution circuitry to output a clock signal that establishes a first timing domain within the integrated circuit component; a timing signal input to receive a data-timing signal from a source external to the integrated circuit component, the data-timing signal having (i) a time-varying phase offset relative to the first timing domain, and (ii) active timing transitions that are preceded by one or more preamble transitions and succeeded by one or more postamble transitions; and timing-signal gating circuitry to: generate a gating pulse that drifts relative to the first timing domain in accordance with the time-varying phase offset; and gate the data-timing signal with the gating pulse to generate a gated timing signal that lacks the one or more preamble transitions and the one or more postamble transitions.
2. 2 . The integrated circuit component of claim 1 wherein the timing signal input to receive the data-timing signal from the source external to the integrated circuit component comprises an input to receive the data-timing signal from a dynamic random access memory (DRAM) component, the integrated circuit component further comprising a timing interface to output the clock signal to the DRAM component.
3. 3 . The integrated circuit component of claim 1 wherein the source external to the integrated circuit component comprises a dynamic random access memory (DRAM) component and wherein the integrated circuit component further comprises: a command interface to output, to the DRAM component, a memory read command that instructs the DRAM component to transmit a read data signal to the integrated circuit component; and a data interface to sample the read data signal synchronously with respect to the gated timing signal.
4. 4 . The integrated circuit component of claim 3 wherein the data interface to sample the read data signal synchronously with respect to the gated timing signal comprises circuitry to sample the read data signal in response to successive edges of the gated timing signal.
5. 5 . The integrated circuit component of claim 1 wherein the timing-signal gating circuitry to generate the gating pulse that drifts relative to the first timing domain in accordance with the time-varying phase offset comprises a first-in-first-out (FIFO) storage structure to store qualification values corresponding to respective pairs of edges expected within the data-timing signal and to sequentially output the qualification values during respective cycles of the timing strobe signal.
6. 6 . The integrated circuit component of claim 5 wherein the timing-signal gating circuitry to generate the gating pulse that drifts relative to the first timing domain in accordance with the time-varying phase offset further comprises logic circuitry to selectively generate a leading edge of the gating pulse during the respective cycles of the data-timing signal according to the qualification values output from the FIFO storage structure.
7. 7 . The integrated circuit component of claim 1 further comprising control circuitry to supply first and second control signals to the timing-signal gating circuitry, the first control signal indicating a total number of edges expected within the data-timing signal in association with the data burst, including the active strobe edges and edges within the preamble and postamble waveforms, and the second control signal indicating a number of the active strobe edges expected within the data-timing signal in association with the data burst, and wherein the timing-signal gating circuitry to generate the gating pulse that drifts relative to the first timing domain in accordance with the time-varying phase offset comprises circuitry to generate the gating pulse based at least in part on the first and second control signals.
8. 8 . The integrated circuit component of claim 1 wherein the timing-signal gating circuitry to generate the gating pulse that drifts relative to the first timing domain in accordance with the time-varying phase offset comprises circuitry to generate, as the gating pulse, a gating signal that transitions to an enable state following a final one of the preamble transitions and then to a disable state prior to an initial one of the postamble transitions.
9. 9 . The integrated circuit component of claim 1 wherein the preamble transitions constitute at least part of a preamble waveform within the data-timing signal, the integrated circuit component further comprising circuitry to generate a first mode signal indicative of one or more characteristics of the preamble waveform, and wherein the timing-signal gating circuitry comprises circuitry to assert a leading edge of the gating pulse at a time based, at least in part, on the first mode signal.
10. 10 . The integrated circuit component of claim 1 wherein the timing-signal gating circuitry to gate the data-timing signal with the gating pulse comprises a logic circuit to logically AND the gating pulse and the data-timing signal to produce the gated timing signal.
11. 11 . A method of operation within an integrated circuit component, the method comprising: outputting, via clock distribution circuitry, a clock signal that establishes a first timing domain within the integrated circuit component; receiving, from a source external to the integrated circuit component, a data-timing signal having (i) a time-varying phase offset relative to the first timing domain, and (ii) active timing transitions that are preceded by one or more preamble transitions and succeeded by one or more postamble transitions; generating a gating pulse that drifts relative to the first timing domain in accordance with the time-varying phase offset; and gating the data-timing signal with the gating pulse to generate a gated timing signal that lacks the one or more preamble transitions and the one or more postamble transitions.
12. 12 . The method of claim 11 wherein receiving the data-timing signal from the source external to the integrated circuit component comprises receiving the data-timing signal from a dynamic random access memory (DRAM) component, the method further comprising outputting the clock signal from the integrated circuit component to the DRAM component.
13. 13 . The method of claim 11 wherein the source external to the integrated circuit component comprises a dynamic random access memory (DRAM) component and wherein the method further comprises: outputting, to the DRAM component, a memory read command that instructs the DRAM component to transmit a read data signal to the integrated circuit component; and sampling the read data signal synchronously with respect to the gated timing signal.
14. 14 . The method of claim 13 wherein sampling the read data signal synchronously with respect to the gated timing signal comprises sampling the read data signal in response to successive edges of the gated timing signal.
15. 15 . The method of claim 11 wherein generating the gating pulse that drifts relative to the first timing domain in accordance with the time-varying phase offset comprises (i) storing, within a first-in-first-out (FIFO) storage structure, qualification values corresponding to respective pairs of edges expected within the data-timing signal, and (ii) sequentially outputting the qualification values from the FIFO storage structure during respective cycles of the timing strobe signal.
16. 16 . The method of claim 15 wherein generating the gating pulse that drifts relative to the first timing domain in accordance with the time-varying phase offset further comprises selectively generating a leading edge of the gating pulse during the respective cycles of the data-timing signal according to the qualification values output from the FIFO storage structure.
17. 17 . The method of claim 11 further comprising generating (i) first control signal indicating a total number of edges expected within the data-timing signal in association with the data burst, including the active strobe edges and edges within the preamble and postamble waveforms, and (ii) a second control signal indicating a number of the active strobe edges expected within the data-timing signal in association with the data burst, and wherein generating the gating pulse that drifts relative to the first timing domain in accordance with the time-varying phase offset comprises generating the gating pulse based at least in part on the first and second control signals.
18. 18 . The method of claim 11 wherein generating the gating pulse that drifts relative to the first timing domain in accordance with the time-varying phase offset comprises generating, as the gating pulse, a gating signal that transitions to an enable state following a final one of the preamble transitions and then to a disable state prior to an initial one of the postamble transitions.
19. 19 . The method of claim 11 wherein the preamble transitions constitute at least part of a preamble waveform within the data-timing signal, the method further comprising generating a first mode signal indicative of one or more characteristics of the preamble waveform, and wherein generating the gating pulse comprises asserting a leading edge of the gating pulse at a time based, at least in part, on the first mode signal.
20. 20 . The method of claim 11 wherein gating the data-timing signal with the gating pulse comprises logically AND the gating pulse and the data-timing signal to produce the gated timing signal.

Description

CROSS REFERENCE TO RELATED APPLICATIONS This application is a continuation of U.S. application Ser. No. 18/234,288 filed Aug. 15, 2023 (U.S. Pat. No. 12,062,413), which is a continuation of U.S. application Ser. No. 17/458,215 filed Aug. 26, 2021 (U.S. Pat. No. 11,763,865), which is a continuation of U.S. application Ser. No. 16/995,612 filed Aug. 17, 2020 (U.S. Pat. No. 11,127,444), which claims the benefit of U.S. Provisional Application No. 62/889,537 filed Aug. 20, 2019. Each of the above-specified patent applications is hereby incorporated by reference. TECHNICAL FIELD The present disclosure relates to the field of chip-to-chip signaling; signaling between integrated circuit devices. BACKGROUND In strobe-timed signaling systems, “active” strobe edges that mark data sampling instants are preceded and succeeded by characteristic strobe preamble and postamble waveforms having idle-to-ready transitions and vice-versa—overhead transitions that are removed (“gated out”) from the timing signal supplied to trigger signal sampling operations within link receivers. The interval between preamble transition and the first active strobe edge (and/or final active strobe edge and postamble transition) may be as brief as a bit-time, imposing tight assertion/deassertion timing margins for the “gate” signal used to frame (pass) active strobe edges and block overhead (non-active) strobe edges. Gate signal generation is further complicated by time-varying skew between the incoming strobe/data ensemble and the internal clock domain of the receiving chip—phase lead or lag that may drift beyond one or more bit-time intervals—and by data access protocols in which successive data bursts may follow one another so closely as to leave insufficient time for complete strobe postamble and/or preamble waveforms. DRAWINGS The various embodiments disclosed herein are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to similar elements and in which: FIG. 1 illustrates a generalized embodiment of a chip-to-chip signaling system in which an integrated-circuit (IC) memory component implements adaptive strobe gating to receive strobe-timed data signals from an integrated-circuit memory control component; FIG. 2 illustrates various characteristic waveforms that may be conveyed to the memory component of FIG. 1 via DQ and DQS signaling links under different burst-separation and skew conditions; FIG. 3 illustrates a conceptual embodiment of a gate synthesizer circuit intended for operation with a toggling preamble and that may be used to implement the gate synthesizer shown in FIG. 1; FIG. 4 illustrates a more detailed embodiment of a gate synthesizer having feature-search, switchover and toggle-qualifier components together with an enable-select multiplexer and re-timing flop stage; FIG. 5A illustrates exemplary control signal waveforms, channel waveforms and gate synthesis waveforms corresponding to the FIG. 4 gate synthesizer under nominal timing conditions for a single-toggle, three-cycle preamble; FIG. 5B illustrates the skew tolerance of the FIG. 4 gate synthesizer, showing the gate opening operation when the strobe/data ensemble is skewed to early and late extremes within the tolerable skew range; FIG. 6A illustrates exemplary operation of the FIG. 4 gate synthesizer under an interamble condition; FIG. 6B illustrates an alternative operation of the FIG. 4 gate synthesizer in an embodiment that resets the write pointer and toggle qualifier content to logic ‘1’ states instead of logic ‘0’ states; and FIGS. 7 and 8 illustrate exemplary generation of the control signals supplied to enable feature-search, enable-domain switchover and toggle qualification within the gate synthesizer of FIG. 3 (or any gate synthesizer embodiments herein) under different burst-separation scenarios. DETAILED DESCRIPTION In various embodiments disclosed herein, a strobe gating signal is generated adaptively based on timing events in the incoming strobe signal itself to yield a gating window that opens and closes deterministically with respect to active edges of the strobe signal. In a number of embodiments, the gating signal is asserted in response to a qualified transition or logic level in the strobe preamble that precedes the first active strobe edge and then deasserted in response to the final active strobe edge, thus effecting a gating window that drifts—relative to the receive-side timing domain—with the strobe signal itself. Further, qualification of the preamble feature (transition or logic level according to preamble type) that triggers gate-signal assertion is implemented by either of two alternate gate-enable signals according to traffic conditions—one gate-enable timed by a reference clock within the receive-side timing domain and the other timed by edges of the strobe signal itself and thus aligned with the strobe timing domain. More specifically, where