US-12626741-B2 - Write driver with selective voltage swing for memory devices

Abstract

A write driver for performing a write operation on a semiconductor memory device includes a first pull-up circuit, a second pull-up circuit and a pull-down circuit. The first pull-up circuit is connected to an output terminal, and pulls up the output terminal based on a power supply voltage and a first pull-up control signal. The second pull-up circuit is connected to the output terminal, and pulls up the output terminal based on the power supply voltage and a second pull-up control signal. The pull-down circuit is connected to the output terminal, and pulls down the output terminal based on a ground voltage and a pull-down control signal. A first pull-up operation for pulling up the output terminal using the first pull-up circuit, and a second pull-up operation for pulling up the output terminal using the second pull-up circuit are selectively performed.

Inventors

• Jaeyoul LEE
• Sanghoon Jung
• Jinyong Choi

Assignees

• SAMSUNG ELECTRONICS CO., LTD.

Dates

Publication Date

20260512

Application Date

20240531

Priority Date

20231201

Claims (18)

1. 1 . A write driver configured to perform a write operation on a semiconductor memory device, the write driver comprising: a first pull-up circuit connected to an output terminal, the first pull-up circuit configured to pull up a voltage level of the output terminal based on a power supply voltage and a first pull-up control signal; a second pull-up circuit connected to the output terminal, the second pull-up circuit configured to pull up the voltage level of the output terminal based on the power supply voltage and a second pull-up control signal; and a pull-down circuit connected to the output terminal, the pull-down circuit configured to pull down the voltage level of the output terminal based on a ground voltage and a pull-down control signal, and wherein a first pull-up operation for pulling up the voltage level of the output terminal using the first pull-up circuit, and a second pull-up operation for pulling up the voltage level of the output terminal using the second pull-up circuit are selectively performed, wherein the write driver is configured to disable the second pull-up circuit while the first pull-up circuit is enabled to perform the first pull-up operation and is further configured to disable the first pull-up circuit while the second pull-up circuit is enabled to perform the second pull-up operation.
2. 2 . The write driver of claim 1 , wherein a first swing width of a voltage at the output terminal during the first pull-up operation is smaller than a second swing width of a voltage at the output terminal during the second pull-up operation.
3. 3 . The write driver of claim 1 , wherein the first pull-up circuit and the second pull-up circuit include different types of transistors.
4. 4 . The write driver of claim 3 , wherein the first pull-up circuit includes: a first n-type metal oxide semiconductor (NMOS) transistor connected between a power supply terminal receiving the power supply voltage and the output terminal, the first NMOS transistor including a first NMOS gate electrode to which the first pull-up control signal is applied.
5. 5 . The write driver of claim 4 , wherein the second pull-up circuit includes: a p-type metal oxide semiconductor (PMOS) transistor connected between the power supply terminal and the output terminal, the PMOS transistor including a PMOS gate electrode to which the second pull-up control signal is applied.
6. 6 . The write driver of claim 5 , wherein the first NMOS transistor and the PMOS transistor are configured to operate based on the power supply voltage that is maintained at the same voltage.
7. 7 . The write driver of claim 4 , wherein the first pull-up circuit and the pull-down circuit include the same type of transistors.
8. 8 . The write driver of claim 7 , wherein the pull-down circuit includes: a second NMOS transistor connected between the output terminal and a ground terminal receiving the ground voltage, the second NMOS transistor including a second NMOS gate electrode to which the pull-down control signal is applied.
9. 9 . The write driver of claim 1 , wherein the write operation is an operation in which a plurality of data that are consecutive data are stored in the semiconductor memory device at once.
10. 10 . The write driver of claim 9 , wherein, in a time interval during which the plurality of data are provided, the first pull-up operation is performed during a first portion of the time interval, and the second pull-up operation is performed during a second portion of the time interval subsequent to the first portion of the time interval.
11. 11 . The write driver of claim 10 , wherein a length of the second portion of the time interval is changeable.
12. 12 . The write driver of claim 10 , wherein, among the plurality of data, a number of data provided during the second portion of the time interval is changeable.
13. 13 . The write driver of claim 10 , wherein the pull-down circuit is configured to perform a pull-down operation for pulling down the voltage level of the output terminal during the first portion of the time interval and the second portion of the time interval.
14. 14 . The write driver of claim 10 , wherein the first portion of the time interval and the second portion of the time interval do not overlap with each other.
15. 15 . A semiconductor memory device comprising: a memory cell array including a plurality of memory cells connected to a plurality of wordlines and a plurality of bitlines; a plurality of bitline sense amplifiers connected to the memory cell array through the plurality of bitlines; and a plurality of write drivers connected to the plurality of bitline sense amplifiers through a plurality of global input/output (I/O) lines, the plurality of write drivers configured to perform a write operation on the memory cell array, wherein each of the plurality of write drivers includes: a first pull-up circuit connected to an output terminal, the first pull-up circuit configured to pull up a voltage level of the output terminal based on a power supply voltage and a first pull-up control signal; a second pull-up circuit connected to the output terminal, the second pull-up circuit configured to pull up the voltage level of the output terminal based on the power supply voltage and a second pull-up control signal; and a pull-down circuit connected to the output terminal, the pull-down circuit configured to pull down the voltage level of the output terminal based on a ground voltage and a pull-down control signal, and wherein a first pull-up operation for pulling up the voltage level of the output terminal using the first pull-up circuit, and a second pull-up operation for pulling up the voltage level of the output terminal using the second pull-up circuit are selectively performed, wherein the plurality of memory cells include a first memory cell and a second memory cell, wherein the plurality of write drivers include a first write driver connected to the first memory cell, and a second write driver connected to the second memory cell, and wherein a length of a first time interval during which the first write driver performs the second pull-up operation and a length of a second time interval during which the second write driver performs the second pull-up operation are different from each other, depending on a first distance between the first memory cell and the first write driver and a second distance between the second memory cell and the second write driver.
16. 16 . The semiconductor memory device of claim 15 , further comprising: a plurality of column selection line drivers configured to control electrical connections between the plurality of bitlines and the plurality of global I/O lines, and wherein output terminals of the plurality of write drivers are connected to the plurality of global I/O lines.
17. 17 . The semiconductor memory device of claim 15 , wherein the semiconductor memory device is a dynamic random access memory (DRAM) device.
18. 18 . A write driver configured to perform a write operation on a semiconductor memory device, the write driver comprising: a first n-type metal oxide semiconductor (NMOS) transistor connected between a power supply terminal receiving a power supply voltage and an output terminal connected to a global input/output (I/O) line, the first NMOS transistor including a gate electrode to which a first pull-up control signal is applied; a p-type metal oxide semiconductor (PMOS) transistor connected between the power supply terminal and the output terminal, the PMOS transistor including a gate electrode to which a second pull-up control signal is applied; a second NMOS transistor connected between the output terminal and a ground terminal receiving a ground voltage, the second NMOS transistor including a gate electrode to which a pull-down control signal is applied, wherein the write operation is an operation in which a plurality of data that are consecutive data are stored in the semiconductor memory device at once, wherein, in a time interval during which the plurality of data are provided, a first pull-up operation for pulling up a voltage level of the output terminal based on the power supply voltage and the first pull-up control signal is performed during a first portion of the time interval, a second pull-up operation for pulling up the voltage level of the output terminal based on the power supply voltage and the second pull-up control signal is performed during a second portion of the time interval subsequent to the first portion of the time interval, and a pull-down operation for pulling down the voltage level of the output terminal based on the ground voltage and the pull-down control signal is performed during the first portion of the time interval and the second portion of the time interval, wherein, in the first portion of the time interval, the PMOS transistor is disabled, and a voltage at the output terminal has a first swing width based on the first pull-up operation and the pull-down operation, and wherein, in the second portion of the time interval, the first NMOS transistor is disabled, and the voltage at the output terminal has a second swing width greater than the first swing width based on the second pull-up operation and the pull-down operation.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application claims priority under 35 USC § 119 to Korean Patent Application No. 10-2023-0172037 filed on Dec. 1, 2023 in the Korean Intellectual Property Office (KIPO), the contents of which are herein incorporated by reference in their entirety. BACKGROUND 1. Technical Field Example embodiments relate generally to semiconductor integrated circuits, and more particularly to write drivers, and semiconductor memory devices including the write drivers. 2. Description of the Related Art Semiconductor memory devices may be divided into two categories depending upon whether or not they retain stored data when disconnected from a power supply. These categories include volatile memory devices, which lose stored data when disconnected from power, and nonvolatile memory devices, which retain stored data when disconnected from power. While volatile memory devices may perform read and write operations at a high speed, contents stored therein may be lost at power-off. Since nonvolatile memory devices retain contents stored therein even at power-off, they may be used to store data that needs to be retained. Various structures are being adopted to increase the density of semiconductor memory devices and reduce the size of semiconductor memory devices. In addition, various structures are being adopted to increase the operating speed of semiconductor memory devices and reduce the power consumption of semiconductor memory devices. Various methods are being studied to achieve all of the above-mentioned objectives. Various methods are being studied to achieve all of the above-mentioned objectives. SUMMARY At least one example embodiment of the present disclosure provides a write driver capable of efficiently reducing power consumption as well as writing time. At least one example embodiment of the present disclosure provides a write driver capable of efficiently reducing power consumption while increasing the speed of write operations. According to example embodiments, a write driver performing a write operation on a semiconductor memory device includes a first pull-up circuit, a second pull-up circuit and a pull-down circuit. The first pull-up circuit is connected to an output terminal, and pulls up the output terminal based on a power supply voltage and a first pull-up control signal. The second pull-up circuit is connected to the output terminal, and pulls up the output terminal based on the power supply voltage and a second pull-up control signal. The pull-down circuit is connected to the output terminal, and pulls down the output terminal based on a ground voltage and a pull-down control signal. A first pull-up operation for pulling up the output terminal using the first pull-up circuit, and a second pull-up operation for pulling up the output terminal using the second pull-up circuit are selectively performed. According to example embodiments, a semiconductor memory device includes a memory cell array, a plurality of bitline sense amplifiers and a plurality of write drivers. The memory cell array includes a plurality of memory cells connected to a plurality of wordlines and a plurality of bitlines. The plurality of bitline sense amplifiers are connected to the memory cell array through the plurality of bitlines. The plurality of write drivers are connected to the plurality of bitline sense amplifiers through a plurality of global input/output (I/O) lines, and perform a write operation on the memory cell array. Each of the plurality of write drivers includes a first pull-up circuit, a second pull-up circuit and a pull-down circuit. The first pull-up circuit is connected to an output terminal, and pulls up the output terminal based on a power supply voltage and a first pull-up control signal. The second pull-up circuit is connected to the output terminal, and pulls up the output terminal based on the power supply voltage and a second pull-up control signal. The pull-up the output terminal using the first pull-up circuit, and a second pull-up operation for pulling up the output terminal using the second pull-up circuit are selectively performed. As used herein, references to “pulling up,” “pulls up,” or a “pull-up” of a particular terminal refer to pulling up a voltage at the particular terminal to a higher voltage level, and do not imply a physical movement of the terminal itself. Similarly, references to “pulling down,” “pulls down,” or a “pull-down” of a particular terminal refer to pulling down a voltage at the particular terminal to a lower voltage level, and do not imply a physical movement of the terminal itself. According to example embodiments, a write driver performing a write operation on a semiconductor memory device includes a first n-type metal oxide semiconductor (NMOS) transistor, a p-type metal oxide semiconductor (PMOS) transistor and a second NMOS transistor. The first NMOS transistor is connected between a power supply terminal receiving a power supply voltage