US-12626742-B2 - Systems and methods for ensuring high read reliability in pre-programmed memory cells

US12626742B2US 12626742 B2US12626742 B2US 12626742B2US-12626742-B2

Abstract

To increase read reliability margins in read-only MRAM arrays, a complimentary pair of MRAM cells includes a first MRAM cell having a first resistance value within a first “high” resistance range R H and storing a logic “HI” value and a second “shorted” MRAM cell having a second resistance value within a second “minimal” resistance range R o and storing a logic “LO” value. During manufacture and testing, MRAM cells that are assigned logic “LO” values are permanently shorted prior to distribution such that they permanently exhibit resistance values within the second “minimal” resistance range R o . When reading the values stored within the complimentary pair of MRAM cells, a differential sense amplifier applies a common reference current across the first MRAM cell and the second “shorted” MRAM cell; by shorting cells with logic “LO” values, a system can reliably read logic values stored within the read-only MRAM array.

Inventors

Doug Smith
Sushil Sakhare

Assignees

Veevx, Inc.

Dates

Publication Date: 20260512
Application Date: 20230822

Claims (14)

1 . A memory unit, comprising: a first memory cell of a read-only memory array including a first magnetic tunnel junction device having a fixed layer, a free layer, and a barrier layer positioned between the fixed layer and the free layer, the free layer having an antiparallel magnetic dipole orientation relative to the fixed layer such that the first memory cell exhibits a first resistance value and stores a first logic value; a second memory cell of the read-only memory array including a second magnetic tunnel junction device having a fixed layer, a free layer, and a barrier layer positioned between the fixed layer and the free layer, wherein the barrier layer of the second magnetic tunnel junction device is shorted such that the second memory cell permanently exhibits a second resistance value and maintains a second logic value; a first plurality of bit lines, the first plurality of bit lines including a first bit line coupled to the first memory cell; a second plurality of bit lines, the second plurality of bit lines including a second bit line coupled to the second memory cell; and a multiplexer in communication with a differential sensing amplifier, the multiplexer being configured to selectively establish electrical communication between a selected one of the first plurality of bit lines and a first input node of the differential sensing amplifier and between a selected one of the second plurality of bit lines and a second input node of the differential sensing amplifier and, during a read operation of a selected bit value of the read-only memory array, to (i) selectively couple the first bit line from the first plurality of bit lines to the first input node and (ii) selectively couple the second bit line from the second plurality of bit lines to the second input node such that the first memory cell and the second memory cell together form a complementary cell pair that stores a single bit value of a read-only memory array, and the differential sensing amplifier being configured to: bias the complementary cell pair such that a first output voltage at the first input node depends on the first resistance value and a second output voltage at the second input node depends on the second resistance value; and measure a differential voltage value between the first output voltage and the second output voltage, wherein the barrier layer of the second magnetic tunnel junction device being shorted and the free layer of the first magnetic tunnel junction device having the antiparallel magnetic dipole orientation relative to the fixed layer such that the first resistance value is greater than the second resistance value results in maximization of the differential voltage value during the read operation.
2 . The memory unit of claim 1 , wherein the second magnetic tunnel junction device of the second memory cell is shorted by application of a shorting voltage or current having a value within a shorting voltage or current range across the free layer and the fixed layer.
3 . The memory unit of claim 1 , the first memory cell further comprising: a first access transistor including a first drain contact, a first source contact, and a first gate contact, wherein the first source contact is in electrical communication with a source line and wherein the first gate contact is in electrical communication with a word line; wherein the fixed layer of the first magnetic tunnel junction device is in electrical communication with the first drain contact of the first access transistor and the free layer of the first magnetic tunnel junction device is in electrical communication with the first bit line.
4 . The memory unit of claim 1 , the second memory cell further comprising: a second access transistor including a second drain contact, a second source contact, and a second gate contact, wherein the second source contact is in electrical communication with a source line and wherein the second gate contact is in electrical communication with a word line; wherein the fixed layer of the second magnetic tunnel junction device of the second memory cell is in electrical communication with the second drain contact of the second access transistor and the free layer of the second magnetic tunnel junction device of the second memory cell is in electrical communication with the second bit line.
5 . The memory unit of claim 1 , wherein the first memory cell or the second memory cell further includes a third magnetic tunnel junction device connected in series or in parallel with the first magnetic tunnel junction device such that the first memory cell or the second memory cell exhibits a target total resistance value R target .
6 . A method, comprising: configuring a read-only memory array and a multiplexer in communication with a differential sensing amplifier, the read-only memory array including a first subset of memory cells including a first memory cell storing a first logic value and a second subset of memory cells including a second memory cell storing a second logic value, the first memory cell including a first magnetic tunnel junction device having a fixed layer, a free layer, and a barrier layer positioned between the fixed layer and the free layer, the free layer having an antiparallel magnetic dipole orientation relative to the fixed layer such that the first memory cell exhibits a first resistance value and stores the first logic value, the configuring further comprising: configuring the read-only memory array to include a first plurality of bit lines and a second plurality of bit lines, the first plurality of bit lines including a first bit line coupled to the first memory cell and the second plurality of bit lines including a second bit line coupled to the second memory cell, and configuring the multiplexer to: (i) selectively establish electrical communication between a selected one of the first plurality of bit lines and a first input node of the differential sensing amplifier, and between a selected one of the second plurality of bit lines and a second input node of the differential sensing amplifier and, (ii) during a read operation of a selected bit value of the read-only memory array, to selectively couple the first bit line from the first plurality of bit lines to the first input node and the second bit line from the second plurality of bit lines to the second input node such that the first memory cell and the second memory cell together form a complementary cell pair that stores a single bit value of the read-only memory array; and applying a shorting voltage or current to the second memory cell of the second subset of memory cells of the read-only memory array, the second memory cell including a second magnetic tunnel junction device having a fixed layer, a free layer, and a barrier layer positioned between the fixed layer and the free layer, wherein the barrier layer of the second magnetic tunnel junction device is shorted such that the second memory cell permanently exhibits a second resistance value and maintains the second logic value; wherein the barrier layer of the second magnetic tunnel junction device being shorted and the free layer of the first magnetic tunnel junction device having the antiparallel magnetic dipole orientation relative to the fixed layer such that the first resistance value is greater than the second resistance value results in maximization of a differential voltage value between the first memory cell and the second memory cell during the read operation.
7 . The method of claim 6 , further comprising: configuring the multiplexer to pair each memory cell of the first subset of memory cells with a respective memory cell of the second subset of memory cells.
8 . The method of claim 6 , wherein the differential sensing amplifier is in electrical communication with the first memory cell of the first subset of memory cells and the second memory cell of the second subset of memory cells, the differential sensing amplifier being configured to read a logic value exhibited by the first memory cell or the second memory cell by amplification of a differential voltage associated with a difference between the first resistance value of the first memory cell and the second resistance value of the second memory cell.
9 . The method of claim 6 , further comprising: applying, by the differential sensing amplifier, a reference current to the first memory cell and the second memory cell that results in a first output voltage associated with the first memory cell and a second output voltage associated with the second memory cell, wherein the first output voltage correlates with the first resistance value held by the first memory cell and wherein the second output voltage correlates with the second resistance value held by the second memory cell.
10 . The method of claim 6 , further comprising: applying a testing algorithm to the read-only memory array yielding a first listing of memory cells to be included within the first subset of memory cells and a second listing of memory cells to be included within the second subset of memory cells.
11 . The method of claim 10 , further comprising: applying, during testing of the read-only memory array, a second current to the second subset of memory cells to initially configure the magnetic dipole orientation of the free layer of the second memory cell in a parallel direction with the magnetic dipole orientation of the fixed layer such that the second memory cell stores the second logic value prior to application of the shorting voltage or current to the second memory cell.
12 . The method of claim 6 , wherein the first memory cell or the second memory cell further includes a third magnetic tunnel junction device connected in series or in parallel with the first magnetic tunnel junction device or the second magnetic tunnel junction device such that the first memory cell or the second memory cell exhibits a target total resistance value R target .
13 . The method of claim 6 , further comprising: applying a first current to the first subset of memory cells to store the first logic value at the first memory cell, the first memory cell including a first magnetic tunnel junction device having a fixed layer, a free layer, and a barrier layer positioned between the fixed layer and the free layer, the free layer having an antiparallel magnetic dipole orientation relative to the fixed layer such that the first memory cell exhibits the first resistance value and stores the first logic value.
14 . A memory system comprising: a read-only memory array, including: a first group of memory cells, each comprising a magnetic tunnel junction (MTJ) having an antiparallel magnetic dipole orientation and exhibiting a first resistance value; a second group of memory cells, each comprising an MTJ having a shorted barrier layer and exhibiting a second resistance value that is less than the first resistance value; a first plurality of bit lines, the first plurality of bit lines including a first bit line coupled to a first memory cell of a complementary cell pair, the first memory cell being a member of the first group of memory cells; and a second plurality of bit lines, the second plurality of bit lines including a second bit line coupled to a second memory cell of the complementary cell pair, the second memory cell being a member of the second group of memory cells; a differential sensing circuit including a differential sensing amplifier having a first input node and a second input node; and a mapping circuit including a first multiplexer configured to selectively couple a bit line of the first plurality of bit lines with the first input node of the differential sensing circuit, and a second multiplexer configured to selectively couple a bit line of the second plurality of bit lines with the second input node of the differential sensing circuit, the mapping circuit being further configured to associate respective memory cells of the first group of memory cells with corresponding memory cells of the second group of memory cells as complementary cell pairs, each respective complementary cell pair collectively storing a single bit value of the read-only memory array; and the differential sensing circuit configured to, for each complementary cell pair, bias the complementary cell pair via the first multiplexer and the second multiplexer such that a first signal at the first input node depends on the first resistance value and a second signal at the second input node depends on the second resistance value and to generate the bit value based on a comparison of a differential signal between the first and second signals with a reference current, wherein the antiparallel magnetic dipole orientation of the first group of memory cells and the shorted barrier layer of the second group of memory cells maximizes a magnitude of the differential signal relative to the reference current.

Description

CROSS REFERENCE TO RELATED APPLICATIONS This is a non-provisional application that claims benefit to U.S. Application Ser. No. 63/373,153 filed on Aug. 22, 2022, which is herein incorporated by reference in its entirety. FIELD The present disclosure generally relates to digital memory arrays, and in particular, to a system and associated method for ensuring high read reliability in magnetoresistive random access memory arrays. BACKGROUND Electronic devices often require pre-programmed memory arrays that are tested prior to packaging. Manufacturers determine which memory cells of a pre-programmed memory array need to be fixed at a logic “HI” (e.g., a logic “1”) and which memory cells need to be fixed at a logic “LO” (e.g., a logic “0”) in order to function as intended, and will fix the memory cells of the pre-programmed memory array at the intended logic values. However, electrical properties of memory cells that are intended to hold fixed values within pre-programmed memory arrays can be subject to drift in which memory cells with “HI” values and memory cells with “LO” values can become almost indiscernible from one another, preventing a system from reliably reading data values held within the pre-programmed memory arrays. It is with these observations in mind, among others, that various aspects of the present disclosure were conceived and developed. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A is a simplified illustration showing a conventional MTJ device capable of exhibiting a first logic “HI” value or a second logic “LO” value; FIG. 1B is a graphical representation showing a transfer curve of the MTJ device of FIG. 1A; FIG. 1C is a schematic diagram showing a conventional MRAM cell that includes the MTJ device of FIG. 1A; FIG. 2A is a graphical representation showing a probability density function (PDF) curve of an MTJ device including a minimal resistance range Ro; FIG. 2B is a simplified illustration showing a shorted MTJ device capable of exhibiting a second logic “LO” value and having a resistance value within the minimal resistance range Ro; FIG. 2C is a schematic diagram showing an MRAM cell that includes the shorted MTJ device of FIG. 2B; FIG. 3 is a schematic diagram showing a memory unit employing the shorted MTJ device of FIG. 2B and the MTJ device of FIG. 1A to ensure high read reliability; FIG. 4A is a schematic diagram showing the memory unit of FIG. 3 having a differential sensing amplifier that performs a read operation; FIG. 4B is a graphical representation showing behavior of the differential sensing amplifier during a read cycle; FIGS. 5A-5C are a series of schematic diagrams showing multi-bit MRAM cells employing the shorted MTJ device of FIG. 2B and the MTJ device of FIG. 1A FIG. 6 is a process flow diagram showing a method for configuring a memory unit as shown in FIG. 3 to ensure high read reliability; and FIG. 7 is a simplified schematic diagram illustrating aspects of the method of FIG. 6. Corresponding reference characters indicate corresponding elements among the view of the drawings. The headings used in the figures do not limit the scope of the claims. DETAILED DESCRIPTION Systems and associated methods for ensuring high read reliability in read-only magnetoresistive random access memory (MRAM) arrays are described herein. In particular, a memory unit includes a first memory cell having a first magnetic tunnel junction (MTJ) device that stores a first pre-programmed logic value, and a second memory cell having a second MTJ device that stores a second pre-programmed logic value and is paired with the first memory cell to enable a system to read data values stored within the first memory cell and/or the second memory cell. The first memory cell and the second memory cell are complimentary; for instance, if the first memory cell permanently stores a logic “HI” value, then the second memory cell permanently stores a logic “LO” value, and vice-versa. The second MTJ device of the second memory cell is permanently shorted to ensure that a resistance value across the second MTJ device is at a minimum resistance value, ensuring high read margins between logic values associated with the first MTJ device and the second MTJ device. The memory array can include one or more multiplexers that facilitate pairing of the first memory cell and the second memory cell to ensure that the first memory cell and the second memory cell are complimentary values. Further, the present disclosure provides an example differential sensing amplifier that performs a read operation to read logic values stored within the first MTJ device and the second MTJ device. MTJ Devices With reference to FIG. 1A, an MTJ device 10A has a fixed layer 12A having a first magnetic dipole orientation that is fixed (e.g., permanent), a free layer 14A having a second magnetic dipole orientation that is variable between a first direction (e.g., in alignment with the first magnetic dipole orientation) and a second direction (e.g., opp