US-12626743-B2 - Systems and methods for reading multi-bit MRAM cells

US12626743B2US 12626743 B2US12626743 B2US 12626743B2US-12626743-B2

Abstract

A multi-bit MRAM cell includes at least a first MTJ device storing a first logic bit and a second MTJ device storing a second logic bit. The multi-bit MRAM cell is readable through application of a reference current across the multi-bit MRAM cell and comparison of a resultant output voltage with a plurality of reference voltages.

Inventors

Doug Smith
Sushil Sakhare

Assignees

Veevx, Inc.

Dates

Publication Date: 20260512
Application Date: 20230822

Claims (11)

1 . A circuit, comprising: a reference voltage generation circuit having a plurality of generator legs that concurrently generate first, second, and third reference voltages on respective first, second, and third reference lines; a more significant bit (MSB) stage of a sensing amplifier that, during a clock cycle of a read operation, generates a first complementary output and a second complementary output encoding an MSB result of comparing a voltage across a multi-bit memory unit with the first reference voltage; and a less significant bit (LSB) stage of the sensing amplifier that, during the same clock cycle of the read operation, generates an output encoding an LSB result of comparing the voltage across the multi-bit memory unit with one of the second or third reference voltages, the LSB stage including: a first coupling path between the sensing amplifier and the second reference line gated by the first complementary output of the MSB stage; and a second coupling path between the sensing amplifier and the third reference line gated by the second complementary output of the MSB stage.
2 . The circuit of claim 1 , each respective generator leg including: a first fixed-value magnetic tunnel junction device having a first terminal in electrical communication with a bit line and having a second terminal defined opposite to the first terminal; and a second fixed-value magnetic tunnel junction device connected with the first fixed-value magnetic tunnel junction device in series, the second fixed-value magnetic tunnel junction device having a first terminal in electrical communication with the second terminal of the first fixed-value magnetic tunnel junction device and having a second terminal defined opposite to the first terminal; wherein the first fixed-value magnetic tunnel junction device and the second fixed-value magnetic tunnel junction device contribute to a fixed reference resistance that correlates with a reference voltage of the generator leg.
3 . The circuit of claim 1 , wherein a total resistance value of the multi-bit memory unit correlates with a multi-bit value stored by the multi-bit memory unit.
4 . The circuit of claim 3 , wherein the sensing amplifier compares the output voltage associated with the multi-bit memory unit with the plurality of reference voltages generated by the reference voltage generation circuit to determine the total resistance value of the multi-bit memory unit.
5 . The circuit of claim 3 , wherein the multi-bit value stored by the multi-bit memory unit includes n bits and wherein the reference voltage generation circuit generates 2 2 −1 reference voltages.
6 . The circuit of claim 1 , wherein each generator leg of the plurality of generator legs includes a pull-up transistor network in electrical communication with a positive supply node, the pull-up transistor network including a pull-up transistor having a gate terminal in electrical communication with a corresponding one of the first, second, and third reference lines.
7 . The circuit of claim 6 , wherein a drain terminal of the pull-up transistor of the pull-up transistor network is in electrical communication with the corresponding one of the first, second, and third reference lines.
8 . The circuit of claim 1 , wherein selective combination of two or more generator legs of the plurality of generator legs results in modification of an average voltage of a reference voltage.
9 . The circuit of claim 1 , wherein the first reference voltage is equal to an average of voltages generated by a first generator leg having a fixed-value multi-bit memory unit storing 01 and a second generator leg having a fixed-value multi-bit memory unit storing 10 .
10 . The circuit of claim 1 , wherein the second reference voltage is equal to an average of voltages generated by a third generator leg having a fixed-value multi-bit memory unit storing 10 and a fourth generator leg having a fixed-value multi-bit memory unit storing 11 .
11 . The circuit of claim 1 , wherein the third reference voltage is equal to an average of voltages generated by a fifth generator leg having a fixed-value multi-bit memory unit storing 00 and a sixth generator leg having a fixed-value multi-bit memory unit storing 01 .

Description

CROSS REFERENCE TO RELATED APPLICATIONS This is a non-provisional application that claims benefit to U.S. Provisional Application Ser. No. 63/373,143 filed on Aug. 22, 2022, which is herein incorporated by reference in its entirety. FIELD The present disclosure generally relates to digital memory arrays, and in particular, to a system and associated method for reading data values stored in multi-bit MRAM cells. BACKGROUND Magnetoresistive random access memory (MRAM) cells traditionally store a single bit at a time in a magnetoresistive tunnel junction (MTJ) device; to read the data stored in a single MRAM cell, a resistance across the MTJ device must be measured. While MTJ devices are remarkably small, electronics manufacturers have incentive to continually reduce size and complexity of MRAM arrays. It is with these observations in mind, among others, that various aspects of the present disclosure were conceived and developed. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A is a simplified illustration showing a conventional MTJ device capable of holding a single bit, which can include a first logic “HI” value or a second logic “LO” value; FIG. 1B is a graphical representation showing a transfer curve of the MTJ device of FIG. 1A; FIG. 1C is a schematic diagram showing a conventional MRAM cell that includes the MTJ device of FIG. 1A; FIG. 2A is a schematic diagram showing a multi-bit MRAM cell according to aspects of the present disclosure; FIG. 2B is a graphical representation showing a transfer curve of the multi-bit MRAM cell FIG. 2A; FIG. 2C is a schematic diagram showing a multi-bit MRAM cell extended to n bits; FIG. 2D is a graphical representation showing a transfer curve of the multi-bit MRAM cell FIG. 2C; FIG. 3A is a schematic diagram showing a simplified read circuit for reading the multi-bit MRAM cell of FIG. 2C; FIGS. 3B and 3C are a pair of schematic diagrams respectively showing a first read circuit for reading a most-significant bit (MSB) of the multi-bit MRAM cell of FIG. 2A and a second read circuit for reading a least-significant bit (LSB) of the multi-bit MRAM cell of FIG. 2A; FIG. 3D is a graphical representation showing behavior of the first read circuit and the second read circuit for reading the multi-bit MRAM cell of FIG. 2A during a read cycle; FIG. 4 is a schematic diagram showing reference current generation that enable reading of the multi-bit MRAM cell of FIG. 2A; and FIG. 5 is a process flow diagram showing a method of reading the multi-bit MRAM cell of FIGS. 2A-2D. Corresponding reference characters indicate corresponding elements among the view of the drawings. The headings used in the figures do not limit the scope of the claims. DETAILED DESCRIPTION Systems and associated methods for multi-bit magnetoresistive random access memory (MRAM) cells are described herein. In particular, a multi-bit MRAM cell has at least a first magnetic tunnel junction (MTJ) device that stores a first pre-programmed logic value and a second MTJ device that stores a second pre-programmed logic value, although it should be noted that the MRAM cell can include more than two MTJs for storing more than two bits. The value of the multi-bit MRAM cell can be read by comparison with a plurality of reference voltages; the plurality of reference voltages can be locally-generated as will be described in greater detail herein. MTJ Devices Overview With reference to FIG. 1A, an MTJ device 10 has a fixed layer 12 having a first magnetic dipole orientation that is fixed (e.g., permanent), a free layer 14 having a second magnetic dipole orientation that is variable between a first direction (e.g., in alignment with the first magnetic dipole orientation) and a second direction (e.g., opposite from the first magnetic dipole orientation), and a barrier layer 16 therebetween. The first magnetic dipole orientation of the fixed layer 12 is always fixed along a first direction, and the second magnetic dipole orientation of the free layer 14 can vary between the first direction and a second direction, where the second direction is opposite to the first direction; the second magnetic dipole orientation of the second “free” layer dictates whether the MTJ device 10 holds a logic “HI” value (e.g., a logic “1”) or a logic “LO” value (e.g., a logic “0” value). Typically, the MTJ device 10 stores a logic “HI” value by exhibiting a resistance value within a “high” resistance range RH observed between the fixed layer 12 and the free layer 14 of the MTJ device 10 such that the first magnetic dipole orientation of the fixed layer 12 and the second magnetic dipole orientation of the free layer 14 are opposite from one another. The MTJ device 10 stores a logic “LO” by exhibiting a resistance value within a “low” resistance range RL observed between the fixed layer 12 and the free layer 14 of the MTJ device 10 such that the first magnetic dipole orientation of the fixed layer 12 and the second magnetic dipole orientation of the free layer