US-12626745-B2 - Step voltage during current force read of programmable resistance memory cell with threshold switching selector

US12626745B2US 12626745 B2US12626745 B2US 12626745B2US-12626745-B2

Abstract

Technology for reading memory cells in a cross-point memory array. Each memory cell has a threshold switching selector in series with a programmable resistance memory element. The memory system applies a step voltage pulse during a current force read of programmable resistance memory cells in a cross-bar memory array. In an aspect, the step voltage pulse is used to switch on the threshold switching selector. In an aspect, the step voltage pulse is applied after the threshold switching selector switches on when a snapback current may be present. In an aspect, the step voltage pulse is applied after the snapback current has dissipated.

Inventors

Juan P. Saenz
Michael K. Grobis

Assignees

SanDisk Technologies, Inc.

Dates

Publication Date: 20260512
Application Date: 20240620

Claims (20)

1 . An apparatus comprising: one or more control circuits configured to communicate with a cross-point memory structure having first conductive lines, second conductive lines, and memory cells, each memory cell at a crosspoint of a first conductive line and a second conductive line, each memory cell having a programmable resistance memory element in series with a threshold switching selector; the one or more control circuits configured to: apply a fixed magnitude read current to a selected first conductive line while a selected second conductive line is at a select voltage, the selected first conductive line connected to a selected memory cell; apply a step voltage to the selected first conductive line while the threshold switching selector is on; and sense the selected memory cell after the step voltage is removed from the selected first conductive line and while the fixed magnitude read current is driven through the selected memory cell.
2 . The apparatus of claim 1 , wherein the one or more control circuits are configured to: begin to apply the step voltage to the selected first conductive line prior to the threshold switching selector turning on; and continue to apply the step voltage to the selected first conductive line after the threshold switching selector has turned on.
3 . The apparatus of claim 1 , wherein the one or more control circuits are configured to: begin to apply the step voltage to the selected first conductive line after the threshold switching selector of the selected memory cell turns on as a result of applying the fixed magnitude read current to the selected first conductive line.
4 . The apparatus of claim 3 , wherein the one or more control circuits are further configured to: apply the step voltage to the selected first conductive line while a snapback current is present, the snapback current due to a voltage drop across the threshold switching selector after the threshold switching selector switches on.
5 . The apparatus of claim 3 , wherein the one or more control circuits are configured to: begin to apply the step voltage to the selected first conductive line after a snapback current has dissipated, the snapback current due to a voltage drop across the threshold switching selector after the threshold switching selector switches on.
6 . The apparatus of claim 1 , wherein the one or more control circuits are configured to: apply the step voltage to the selected first conductive line while a snapback current is present, the snapback current due to a voltage drop across the threshold switching selector after the threshold switching selector switches on.
7 . The apparatus of claim 1 , wherein the one or more control circuits are further configured to: begin to apply the step voltage to the selected first conductive line after a snapback current has dissipated, the snapback current due to a voltage drop across the threshold switching selector after the threshold switching selector switches on.
8 . The apparatus of claim 1 , wherein the programmable resistance memory element comprises an MRAM element.
9 . The apparatus of claim 1 , wherein the threshold switching selector comprises an Ovonic Threshold Switch (OTS).
10 . The apparatus of claim 1 , wherein the step voltage comprises a step up voltage pulse.
11 . The apparatus of claim 1 , wherein the step voltage comprises a step down voltage pulse.
12 . The apparatus of claim 1 , wherein the step voltage comprises a power supply voltage.
13 . A method for reading a programmable resistance memory cell in a cross-point memory array, the method comprising: applying a fixed magnitude read current to a selected first conductive line in the cross-point memory array while a selected second conductive line is at a select voltage, the fixed magnitude read current creates a voltage across a selected memory cell between the selected first conductive line and the selected second conductive line that turns on a threshold switching selector of the selected memory cell; applying a step voltage pulse to the selected first conductive line after the threshold switching selector turns on and a snapback current is present; and sensing the selected memory cell while the threshold switching selector is on and the fixed magnitude read current is driven through the selected memory cell.
14 . The method of claim 13 , wherein applying the step voltage pulse to the selected first conductive line comprises applying a step up voltage pulse to the selected first conductive line in response to a voltage across the selected memory cell falling.
15 . The method of claim 13 , wherein applying the step voltage pulse to the selected first conductive line comprises applying a step down voltage pulse to the selected first conductive line in response to a voltage across the selected memory cell falling.
16 . A memory system, comprising: a cross-point memory structure having first conductive lines, second conductive lines, and memory cells, each memory cell at a crosspoint of a first conductive line and a second conductive line, each memory cell having a programmable resistance memory element in series with a threshold switching selector; and one or more control circuits in communication with the cross-point memory structure, the one or more control circuits configured to: apply a fixed magnitude read current to a selected first conductive line while a selected second conductive line is at a select voltage, the fixed magnitude read current creates a voltage across a selected memory cell that turns on the threshold switching selector of the selected memory cell; apply a step voltage pulse to the selected first conductive line after the threshold switching selector turns on; and sense the selected memory cell after the step voltage pulse is removed from the selected first conductive line and while the fixed magnitude read current is driven through the selected memory cell.
17 . The memory system of claim 16 , wherein the one or more control circuits are configured to: apply the step voltage pulse to the selected first conductive line while a snapback current is present, the snapback current due to a voltage drop across the threshold switching selector after the threshold switching selector switches on.
18 . The memory system of claim 16 , wherein the one or more control circuits are configured to: apply the step voltage pulse to the selected first conductive line after a snapback current has dissipated, the snapback current due to a voltage drop across the threshold switching selector after the threshold switching selector switches on.
19 . The memory system of claim 16 , wherein: the select voltage applied to the second selected conductive line is ground; and the one or more control circuits are configured to apply the step voltage pulse to the selected first conductive line as a step-up voltage pulse.
20 . The memory system of claim 16 , wherein: the select voltage applied to the second selected conductive line is a high voltage; and the one or more control circuits are configured to apply the step voltage pulse to the selected first conductive line as a step-down voltage pulse.

Description

BACKGROUND Memory is widely used in various electronic devices such as cellular telephones, digital cameras, personal digital assistants, medical electronics, mobile computing devices, non-mobile computing devices, and data servers. Memory may comprise non-volatile memory or volatile memory. A non-volatile memory allows information to be stored and retained even when the non-volatile memory is not connected to a source of power (e.g., a battery). Non-volatile memory can be made to appear non-volatile at least for a limited time by, external to the memory chip, adding battery back to the power supply. The memory cells may reside in a cross-point memory array. In a memory array with a cross-point type architecture, one set of conductive lines run across the surface of a substrate and another set of conductive lines are formed above the other set of conductive lines running in an orthogonal direction relative to the initial layer. The memory cells are located at the cross-point junctions of the two sets of conductive lines. Cross-point memory arrays are sometimes referred to as cross-bar memory arrays. A programmable resistance memory cell is formed from a material having a programmable resistance. In a binary approach, the programmable resistance memory cell can be programmed into one of two resistance states: high resistance state (HRS) and low resistance state (LRS). In some approaches, more than two resistance states may be used. One type of programmable resistance memory cell is a magnetoresistive random access memory (MRAM) cell. An MRAM cell uses magnetization to represent stored data, in contrast to some other memory technologies that use electronic charges (DRAM) or voltages (SRAM) to store data. A bit of data is written to an MRAM cell by changing the direction of magnetization of a magnetic element (“the free layer”) within the MRAM cell, and a bit is read by measuring the resistance of the MRAM cell, such resistance changing with the direction of magnetization. However, the cross-point memory array may have other types of memory cells. For example, the cross-point memory array may have memory cell of other technologies such as ReRam, PCM (Phase Change Memory), or FeRam. In a cross-point memory array, each memory cell may contain a threshold switching selector in series with the material having the programmable resistance. The threshold switching selector has a high resistance (in an off or non-conductive state) until it is biased to a voltage higher than its threshold voltage (Vt) or current above its threshold current, (It), and until its voltage bias falls below Vhold (“Voffset”) or current below a holding current Ihold. After the Vt is exceeded and while Vhold is exceeded across the threshold switching selector, the threshold switching selector has a relatively lower resistance (in an on or conductive state). The threshold switching selector remains on until its current is lowered below a holding current Ihold, or the voltage is lowered below a holding voltage, Vhold. When this occurs, the threshold switching selector returns to the off (higher) resistance state. To read a memory cell, the threshold switching selector is activated by being turned on before the resistance state of the memory cell is determined. One example of a threshold switching selector is an Ovonic Threshold Switch (OTS). Other examples of threshold switching selectors include, but are not limited to, Volatile Conductive Bridge (VCB), Metal-Insulator-Metal (MIM), or other material that provides a highly non-linear dependence of current on select voltage. A forced current technique can be used for reading or writing a programmable resistance memory cell in a cross-point array whereby a current is driven to the memory cell that is address selected for read or write (“selected memory cell”). The cross-point array is composed of orthogonal wire sets in two or more planes. For example, a current is driven to a selected wire in the X direction while a voltage is applied to selected wire in the Y direction. The current will charge up the voltage across the selected memory cell until the threshold switching selector turns on. Then, while the current is driven through the programmable resistance memory element of the selected memory cell, the voltage across the selected cell is sensed. The switching on of a threshold switching selector can result in a snapback current. Specifically, the voltage across the memory cell drops rapidly after the threshold switching selector turns on, resulting in a snapback current. This snapback current can flow through the programmable resistance memory element, which could potentially change the state of the programmable resistance memory element prior to sensing the memory element bit state; e.g., a read disturb that results in a miss-read. Thus, programmable resistance memory elements such as, but not limited to MRAM elements, could inadvertently and undesirably have their state changed due to snapbac