US-12626746-B2 - Method for manufacturing SRAM memory circuit

Abstract

A method includes forming a first transistor, a second transistor, a third transistor, and a fourth transistor over a substrate, wherein at least the second and third transistors include ferroelectric materials; forming an interlayer dielectric (ILD) layer over the first to fourth transistors; forming a first metal line over the ILD layer to interconnect drains of the second and third transistors and a gate of the fourth transistor; forming a second metal line over the ILD layer to interconnect a drain of the first transistor and gates of the second and third transistors; forming a write word line over the ILD layer and electrically connected to a gate of the first transistor but electrically isolated from the fourth transistor; forming a word line over the ILD layer and electrically connected to a source of the first transistor; and forming a bit line electrically connected to the fourth transistor.

Inventors

• Wei-Xiang YOU
• Pin Su
• Kai-Shin Li
• Chenming Hu

Assignees

• TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
• NATIONAL YANG MING CHIAO TUNG UNIVERSITY

Dates

Publication Date

20260512

Application Date

20220726

Claims (20)

1. 1 . A method for manufacturing an SRAM memory circuit, comprising: forming a first MOSFET, a first FeFET, a second FeFET, and a second MOSFET over a substrate, wherein forming the first FeFET comprises: forming a semiconductor fin over the substrate; and forming a gate structure over the semiconductor fin, wherein the gate structure comprises: a ferroelectric layer over the semiconductor fin; and a gate electrode over the ferroelectric layer; and forming a plurality of interconnect layers over the first MOSFET, the first FeFET, the second FeFET, and the second MOSFET, wherein forming the plurality of interconnect layers comprises: forming a first metal line over the substrate to interconnect a drain of the first MOSFET, the gate structure of the first FeFET, and a gate structure of the second FeFET; and forming a second metal line over the substrate to interconnect drains of the first FeFET and the second FeFET and a gate structure of the second MOSFET, such that the first MOSFET, the first FeFET, the second FeFET, the second MOSFET, and the plurality of interconnect layers form the SRAM memory circuit.
2. 2 . The method of claim 1 , wherein the ferroelectric layer is in contact with the semiconductor fin.
3. 3 . The method of claim 1 , wherein the gate structure further comprises a metal layer between the ferroelectric layer and the semiconductor fin.
4. 4 . The method of claim 1 , wherein a remnant polarization (P r ) and a coercive field (E c ) of the ferroelectric layer are not zero.
5. 5 . The method of claim 1 , wherein the gate structure further comprises an interfacial layer between the ferroelectric layer and the semiconductor fin.
6. 6 . The method of claim 5 , wherein a charge density at an interface between the semiconductor fin and the interfacial layer is greater than about 10 9 cm −2 .
7. 7 . The method of claim 1 , wherein a thickness of the ferroelectric layer is in a range between about 1 nm and about 30 nm.
8. 8 . A method for manufacturing an SRAM memory circuit, comprising: forming a first MOSFET, a first FeFET, a second FeFET, and a second MOSFET over a substrate; and forming a plurality of interconnect layers over the first MOSFET, the first FeFET, the second FeFET, and the second MOSFET to form the SRAM memory circuit, wherein forming the plurality of interconnect layers comprises: forming a first metal line over the substrate to interconnect a drain of the first MOSFET and gates of the first FeFET and the second FeFET; forming a second metal line over the substrate to interconnect drains of the first FeFET and the second FeFET and a gate of the second MOSFET; and forming a write word line over the substrate and electrically connected to a gate of the first MOSFET but electrically isolated from the second MOSFET.
9. 9 . The method of claim 8 , wherein the gate of the first MOSFET is free from ferroelectric materials.
10. 10 . The method of claim 8 , wherein forming the plurality of interconnect layers further comprises: forming a word line over the substrate and electrically connected to a source of the first MOSFET but electrically isolated from the second MOSFET.
11. 11 . The method of claim 8 , wherein forming the plurality of interconnect layers further comprises: forming a source line over the substrate and electrically connected to a source of the second MOSFET but electrically isolated from the first MOSFET.
12. 12 . The method of claim 8 , wherein the first FeFET comprises: a semiconductor fin over the substrate; a ferroelectric layer over the semiconductor fin; and a work function adjustment layer over the ferroelectric layer.
13. 13 . The method of claim 12 , wherein the first FeFET further comprises: an interfacial layer between the semiconductor fin and the ferroelectric layer, wherein a thickness of the ferroelectric layer is greater than a thickness of the interfacial layer.
14. 14 . A method for manufacturing an SRAM memory circuit, comprising: forming a first MOSFET, a first FeFET, a second FeFET, and a second MOSFET over a substrate; and forming a plurality of interconnect layers to interconnect the first MOSFET, the first FeFET, the second FeFET, and the second MOSFET, wherein forming the plurality of interconnect layers comprises: forming a first metal line over the substrate to interconnect a drain of the first FeFET and a drain of the second FeFET and a gate of the second MOSFET; and forming a second metal line over the substrate to interconnect a drain of the first MOSFET, a gate of the first FeFET, and a gate of the second FeFET, and a gate of the first MOSFET is electrically isolated from the second MOSFET.
15. 15 . The method of claim 14 , wherein the first FeFET and the second FeFET form an inverter.
16. 16 . The method of claim 14 , wherein forming the plurality of interconnect layers further comprises: forming a word line electrically connected to a source of the first MOSFET; and forming a write word line electrically connected to the gate of the first MOSFET.
17. 17 . The method of claim 14 , wherein forming the plurality of interconnect layers further comprises: forming a bit line electrically connected to a drain of the second MOSFET.
18. 18 . The method of claim 14 , further comprising forming a source line transistor over the substrate prior to forming the plurality of interconnect layers, wherein forming the plurality of interconnect layers to interconnect the first MOSFET, the first FeFET, the second FeFET, and the second MOSFET is further such that a source of the source line transistor is electrically connected to a source of the first FeFET.
19. 19 . The method of claim 14 , further comprising forming a source line transistor over the substrate prior to forming the plurality of interconnect layers, wherein forming the plurality of interconnect layers to interconnect the first MOSFET, the first FeFET, the second FeFET, and the second MOSFET is further such that a drain of the source line transistor is electrically connected to the second MOSFET.
20. 20 . The method of claim 19 , wherein the source line transistor is electrically isolated from the first MOSFET.

Description

PRIORITY CLAIM AND CROSS-REFERENCE This present application is a divisional application of U.S. patent application Ser. No. 16/522,451, filed on Jul. 25, 2019, which is herein incorporated by reference in their entirety. BACKGROUND Generally, memory refers to the physical devices used to store data or programs (sequences of instructions) on a temporary or permanent basis for use in an electronic digital computing device. Computing devices represent information in binary code, written as sequences of 0s and 1s. Each binary digit (or “bit”) may be stored by any physical system that can be in either of two stable states, to represent 0 and 1. This could be an on-off switch, an electrical capacitor that can store or lose a charge, a magnet with its polarity up or down, or a surface that can have a pit or not. Today, capacitors and transistors, functioning as tiny electrical switches, are used for temporary storage, and either disks or tape with a magnetic coating, or plastic discs with patterns of pits are used for long-term storage. Primary computing memory makes use of integrated circuits consisting of silicon-based transistors. There are two main types of memory: volatile and non-volatile. Volatile memory is a kind of computing memory that uses power to maintain the stored information. Most modern semiconductor volatile memory is either Static Random Access Memory (SRAM) or dynamic Random Access Memory (DRAM). SRAM retains its contents as long as the power is connected. SRAM is commonplace in small embedded systems, and it is used in many other systems too. A typical SRAM uses six transistors (6T) to store each memory bit. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. FIG. 1 is a schematic drawing illustrating an exemplary memory circuit according to some embodiments of the present disclosure. FIG. 2 is an enlarge view of the memory cell in FIG. 1. FIG. 3 shows a voltage transfer characteristic (VTC) hysteresis loop of an inverter in FIG. 2 according to some embodiments of the present disclosure. FIG. 4 is a schematic drawing illustrating an exemplary memory circuit at a writing operation according to some embodiments of the present disclosure. FIG. 5 is a schematic drawing illustrating an exemplary memory circuit at a reading operation according to some embodiments of the present disclosure. FIG. 6 is a schematic drawing illustrating an exemplary memory circuit at another reading operation according to some embodiments of the present disclosure. FIG. 7 shows a drain current (Ids) versus gate voltage (Vin) characteristics of a NCFET inverter according to some embodiments of the present disclosure. FIG. 8 is a schematic drawing illustrating an exemplary memory circuit 100′ according to some embodiments of the present disclosure. FIGS. 9A to 17 illustrate a method in various stages of fabricating a memory circuit in accordance with some embodiments of the present disclosure. FIGS. 18A and 18B are perspective views of transistors of the memory circuits according to some embodiments. FIG. 19 is a perspective view of a transistor of the memory circuits according to some embodiments. FIG. 20 is a cross-sectional view along line B-B in FIG. 19. FIGS. 21A and 21B are cross-sectional views of transistors according to some embodiments. FIG. 22 is a performance comparison of the memory circuit of FIG. 1 and a 6T SRAM cell circuit. DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figu