US-12626747-B2 - Semiconductor memory device selectively performing self-refresh operation and self-refresh method thereof

Abstract

A self-refresh method of a semiconductor memory device includes: receiving a self-refresh entry command associated with a self-refresh operation; counting an elapsed time from a time of receiving the self-refresh entry command; and skipping the self-refresh operation depending on whether a self-refresh exit command is received before the counted elapsed time exceeds a reference time.

Inventors

• Youngjae PARK
• Soomin KIM
• Yuchan Kim
• Dongha Kim
• HYUNBO KIM

Assignees

• SAMSUNG ELECTRONICS CO., LTD.

Dates

Publication Date

20260512

Application Date

20240227

Priority Date

20230823

Claims (18)

1. 1 . A self-refresh method of a semiconductor memory device, comprising: receiving a self-refresh entry command associated with a self-refresh operation; counting an elapsed time from a time of receiving the self-refresh entry command; skipping the self-refresh operation depending on whether a self-refresh exit command is received before the counted elapsed time exceeds a reference time; and counting a number of times the self-refresh operation is continuously skipped.
2. 2 . The method of claim 1 , wherein the reference time is shorter than or equal to the refresh period of the semiconductor memory device.
3. 3 . The method of claim 1 , wherein the skipping skips the self-refresh operation when the self-refresh exit command is received before the elapsed time exceeds the reference time.
4. 4 . The method of claim 3 , further comprises executing the self-refresh operation when the self-refresh exit command is not received before the elapsed time exceeds the reference time.
5. 5 . The method of claim 4 , wherein the executing of the self-refresh operation perform an all-bank refresh operation.
6. 6 . The method of claim 5 , wherein the self-refresh operation is terminated in response to receipt of the self-refresh exit command.
7. 7 . The method of claim 1 , further comprising: determining whether the number of times reaches a threshold number; and executing the self-refresh operation when the number of times reaches the threshold number regardless of a time difference between receipt of the self-refresh entry command and the self-refresh exit command.
8. 8 . A semiconductor memory device, comprising: a cell array including a plurality of dynamic-random-access-memory (DRAM) cells; a command decoder configured to decode a command associated with a self-refresh operation to output a self-refresh entry command and a self-refresh exit command; a control circuit configured to generate a control signal to skip the self-refresh operation when a time difference between a reception time of the self-refresh entry command and a reception time of the self-refresh exit command is shorter than a reference time, wherein the control circuit comprises an oscillator duty cycle controller configured to select a period according to a mode register set command and comprising: a lookup table including a plurality of period settings, and a multiplexer configured to select one of the plurality of period setting values in response to a mode register set command to output the period; and a refresh controller configured to perform one of i) the self-refresh operation on a selected memory area of the cell array and ii) the skip of the self-refresh operation, in response to the control signal.
9. 9 . The semiconductor memory device of claim 8 , wherein the control circuit further comprises: a duration detector configured to generate a clock signal according to the selected period and generate the control signal by comparing the time difference with the reference time based on the clock signal.
10. 10 . The semiconductor memory device of claim 9 , wherein the duration detector comprises: an oscillator configured to generate the clock signal according to the selected period; and a counter configured to count elapsed time from the reception time of the self-refresh entry command based on the clock signal, and generate the control signal to skip the self-refresh operation when the self-refresh exit command is received before the elapsed time reaches the reference time.
11. 11 . The semiconductor memory device of claim 8 , wherein the refresh controller performs all-bank refresh operation on a selected memory area in response to activation of the control signal.
12. 12 . The semiconductor memory device of claim 8 , wherein the control circuit activates the control signal regardless of a length of the time difference according to a number of times a self-refresh operation is continuously skipped.
13. 13 . A self-refresh method of a semiconductor memory device, comprising: receiving a self-refresh entry command associated with a self-refresh operation; delaying the self-refresh operation by a reference time in response to the self-refresh entry command; detecting whether a self-refresh exit command is input before an elapsed time from receipt of the self-refresh entry command reaches a reference time; skipping the self-refresh operation when the self-refresh exit command is received before the elapsed time reaches the reference time; and counting a number of times the self-refresh operation is continuously skipped.
14. 14 . The method of claim 13 , wherein the reference time is set based on a refresh period of the semiconductor memory device.
15. 15 . The method of claim 13 , wherein the reference time is selected through a duty cycle adjustment of an internal oscillator set through a mode register set command.
16. 16 . The method of claim 13 , further comprising: executing the self-refresh operation if the self-refresh exit command is not received before the elapsed time reaches the reference time.
17. 17 . The method of claim 16 , further comprising stopping the self-refresh operation in response to receipt of the self-refresh exit command.
18. 18 . The method of claim 13 , further comprising performing the self-refresh operation regardless of a time difference between a reception time of the self-refresh entry command and a reception time of the self-refresh exit command when the counted number of times reaches a threshold number.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This patent application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2023-0110775 filed on Aug. 23, 2023, in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference in its entirety herein. 1. Technical Field Embodiments of the present disclosure described herein are directed to a semiconductor memory device, and more specifically, to a semiconductor memory device that selectively performs a self-refresh operation and a self-refresh method thereof. 2. Discussion of Related Art The semiconductor memory device may be voltage memory such as a dynamic random access memory (DRAM) device, which stores data using charges stored in a capacitor. However, the DRAM device has finite data retention characteristics since the charges stored in the capacitor can leak through various paths over time. Accordingly, the DRAM device uses a refresh operation that periodically rewrites data stored in the capacitor. The refresh of the DRAM device may be performed using DRAM self-refresh commands. For example, a self-refresh of the DRAM device may start in response to a self-refresh entry command and stop in response to a self-refresh exit command. The time between the self-refresh entry command and the self-refresh exit command is defined as the duration of the self-refresh operation. In certain operations, the DRAM self-refresh command may occur unnecessarily. For example, self-refresh entry commands and self-refresh exit commands may be provided frequently without consideration of the duration. A logic error may occur when the self-refresh is forcibly performed repeatedly in situations where self-refresh is not necessary. SUMMARY At least one embodiment of the present disclosure provides a semiconductor memory device that can autonomously perform a self-refresh operation in response to an externally input self-refresh command by considering a self-refresh duration time and a self-refresh method thereof. According to an embodiment, a self-refresh method of a semiconductor memory device includes: receiving a self-refresh entry command associated with a self-refresh operation; counting an elapsed time from a time of receiving the self-refresh entry command; and skipping the self-refresh operation depending on whether a self-refresh exit command is received before the counted elapsed time exceeds a reference time. According to an embodiment, a semiconductor memory device includes a cell array, a command decoder, a control circuit, and a refresh controller. The cell array includes a plurality of dynamic-random-access-memory (DRAM) cells. The command decoder is configured to decode a command associated with a self-refresh operation to generate a self-refresh entry command and a self-refresh exit command. The control circuit is configured to generate a control signal to skip the self-refresh operation when a time difference between a reception time of the self-refresh entry command and a reception time of the self-refresh exit command is shorter than a reference time. The refresh controller is configured to perform one of i) the self-refresh operation on a selected memory area of the cell array and ii) the skip of the self-refresh operation, in response to the control signal. According to an embodiment, a self-refresh method of a semiconductor memory device includes: receiving a self-refresh entry command associated with a self-refresh operation; delaying the self-refresh operation by a reference time in response to the self-refresh entry command; detecting whether a self-refresh exit command is input before an elapsed time from receipt of the self-refresh entry command reaches the reference time; and skipping the self-refresh operation when the self-refresh exit command is received before the elapsed time reaches the reference time. BRIEF DESCRIPTION OF THE FIGURES FIG. 1 is a block diagram showing a memory system including a memory device according to an embodiment of the present invention. FIG. 2 is a block diagram showing a memory device according to an embodiment of the present invention. FIG. 3 is a block diagram showing an operation of a self-refresh skip circuit of the memory device according to an embodiment of the present invention. FIG. 4 is a block diagram showing an oscillator duty cycle controller of FIG. 3 according to an embodiment of the present invention. FIG. 5 is a block diagram showing a duration detector of FIG. 3 according to an embodiment of the present invention. FIG. 6 is a flowchart showing a method of operating the self-refresh skip circuit according to an embodiment of the present invention. FIG. 7 is a timing diagram showing an example operation of the self-refresh skip circuit. FIG. 8 is a timing diagram showing an example operation of the self-refresh skip circuit. FIG. 9 is a flowchart showing a method of operating the self-refresh skip circuit according to an embodiment of the present invention. F