US-12626748-B2 - Voltage generator and memory device including same

US12626748B2US 12626748 B2US12626748 B2US 12626748B2US-12626748-B2

Abstract

A voltage generator including an LDO (low dropout) regulator that supplies a current to an internal voltage node of a sense amplification circuit as feedback control based on a voltage level of the internal voltage node; and a power switch circuit including a plurality of power switches each having one end connected to an external voltage and an opposite end connected to the internal voltage node, and that supplies the current to the internal voltage node as feed-forward control based on a known number of sense amplifiers to be activated. The voltage generator may efficiently supply current according to an operation mode of the sense amplification circuit.

Inventors

Dongil LEE
YOUNGHUN SEO

Assignees

SAMSUNG ELECTRONICS CO., LTD.

Dates

Publication Date: 20260512
Application Date: 20231110
Priority Date: 20221114

Claims (20)

1 . A voltage generator comprising: an LDO regulator configured to supply a first current to an internal voltage node of a sense amplification circuit as feedback control based on a voltage level of the internal voltage node; and a power switch circuit including a plurality of power switches each having one end connected to an external voltage and an opposite end connected to the internal voltage node, and configured to supply a second current to the internal voltage node as feed-forward control based on a number of activated sense amplifiers of the sense amplification circuit.
2 . The voltage generator of claim 1 , wherein the LDO regulator or the power switch circuit is configured to selectively supply the first and second currents to the internal voltage node based on an amount of current consumed by the sense amplification circuit connected to the internal voltage node.
3 . The voltage generator of claim 2 , wherein the power switch circuit is configured to supply the second current to the internal voltage node when executing an offset compensation mode or a sensing mode.
4 . The voltage generator of claim 2 , wherein the LDO regulator is configured to supply the first current to the internal voltage node when executing a precharge mode or a restore mode.
5 . The voltage generator of claim 1 , wherein the power switch circuit comprises a plurality of power switches, and each of the plurality of power switches comprises: a NAND gate configured to receive a mode enable signal and an external voltage code; and a transistor configured to electrically connect the external voltage to the internal voltage node based on an output value of the NAND gate.
6 . The voltage generator of claim 5 , wherein the power switch circuit further comprises a mode selector configured to generate the mode enable signal, and wherein the mode enable signal is activated to a high level when an offset compensation mode and a restore mode are executed.
7 . The voltage generator of claim 6 , wherein the mode selector comprises: an OR gate configured to receive a first pulse signal and a second pulse signal, and output a third pulse signal based on an OR operation on the first pulse signal and the second pulse signal; a delay cell configured to receive the third pulse signal and delay the third pulse signal to output a fourth pulse signal; and an AND gate configured to receive the third pulse signal and the fourth pulse signal, and output the mode enable signal based on an AND operation on the third pulse signal and the fourth pulse signal.
8 . The voltage generator of claim 7 , wherein each of the first pulse signal and the second pulse signal transitions from a low level to a high level at a first time point, and transitions from a high level to a low level at a second time point, and a period between the first time point and the second time point corresponds to an execution period of the offset compensation mode.
9 . The voltage generator of claim 7 , wherein the first pulse signal transitions from a low level to a high level at a first time point, the second pulse signal transitions from a low level to a high level at a second time point later than the first time point, and a period between the first time point and the second time point corresponds to an execution period of a sensing mode.
10 . The voltage generator of claim 5 , wherein the power switch circuit further comprises an external voltage detector configured to generate the external voltage code, and the external voltage detector is configured to generate the external voltage code based on a result of comparing the external voltage with a reference voltage.
11 . The voltage generator of claim 10 , wherein the reference voltage comprises a plurality of reference voltages, and the external voltage detector comprises: a plurality of comparators each configured to receive the external voltage and respective reference voltages from among the plurality of reference voltages having different levels, and provide comparison result values based on the external voltage and the respective reference voltages; and a binary decoder configured to generate the external voltage code by decoding the comparison result values received from the plurality of comparators.
12 . The voltage generator of claim 10 , wherein the external voltage detector comprises: a first delay line corresponding to the external voltage; a second delay line corresponding to the reference voltage; at least one phase detector detecting a phase difference between the first delay line and the second delay line, and providing a phase value output based on the phase difference; a binary decoder outputting a digital signal based on the phase value output from the at least one phase detector; and a D flip-flop that receives the digital signal and outputs the external voltage code in synchronization with an output signal from the first delay line.
13 . The voltage generator of claim 5 , wherein the power switch circuit further comprises an error corrector configured to correct an error of the external voltage code.
14 . The voltage generator of claim 13 , wherein the error corrector comprises a plurality of AND gates and is configured to correct the error of the external voltage code based on a bubble error correction technique.
15 . A memory device comprising: a memory cell array including a plurality of memory cells; a sense amplification circuit configured to read out data stored in the memory cell array; and an internal voltage generator configured to provide an internal voltage to the sense amplification circuit, wherein the internal voltage generator is configured to compensate for a current consumed by the sense amplification circuit by selecting either feedback control or feed-forward control according to an operation mode of the sense amplification circuit, and wherein the internal voltage generator comprises: an LDO regulator configured to supply a first current to an internal voltage node of the sense amplification circuit as the feedback control based on a voltage level of the internal voltage node; and a power switch circuit including a plurality of power switches each having one end connected to an external voltage and an opposite end connected to the internal voltage node, and configured to supply a second current to the internal voltage node as the feed-forward control based on a number of activated sense amplifiers of the sense amplification circuit.
16 . The memory device of claim 15 , wherein the power switch circuit is configured to compensate for the current consumed by the sense amplification circuit when executing an offset compensation mode or a sensing mode.
17 . The memory device of claim 15 , wherein the LDO regulator is configured to compensate for the current consumed by the sense amplification circuit when executing a precharge mode or a restore mode.
18 . The memory device of claim 15 , wherein the power switch circuit comprises a plurality of power switches, and each of the plurality of power switches comprises: a NAND gate configured to receive a mode enable signal and an external voltage code; and a transistor configured to electrically connect the external voltage to the internal voltage node based on an output value of the NAND gate.
19 . The memory device of claim 15 , wherein the power switch circuit further comprises a mode selector configured to generate the mode enable signal, and wherein the mode enable signal is activated to a high level when an offset compensation mode and a restore mode are executed.
20 . The memory device of claim 19 , wherein the mode selector comprises: an OR gate configured to receive a first pulse signal and a second pulse signal, and output a third pulse signal based on an OR operation on the first pulse signal and the second pulse signal; a delay cell configured to receive the third pulse signal and delay the third pulse signal to output a fourth pulse signal; and an AND gate configured to receive the third pulse signal and the fourth pulse signal, and output the mode enable signal based on an AND operation on the third pulse signal and the fourth pulse signal.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2022-0151535 filed on Nov. 14, 2022, in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference herein in its entirety. BACKGROUND The present disclosure relates to voltage generators. Semiconductor memory devices may be implemented using semiconductors such as silicon (Si), germanium (Ge), gallium arsenide (GaAs), indium phosphide (InP), and the like. Semiconductor memory devices may include volatile memory devices and nonvolatile memory devices. A volatile memory device is a memory device in which stored data is lost when power supply is cut off. Volatile memory devices include static RAM (SRAM), dynamic RAM (DRAM), and synchronous DRAM (SDRAM) for example. In volatile memory, normal operations such as a read operation and a refresh operation of periodically rewriting the same data may be performed to maintain integrity of the stored data. In such volatile memory, it is necessary to quickly and stably compensate for the current consumed according to the operation mode. SUMMARY Embodiments of the inventive concepts provide a voltage generator capable of efficiently supplying current according to an operation mode, and a memory device including the same. According to the voltage generator of the inventive concepts, it is possible to efficiently supply current by a load block such as a sense amplifier according to an operation mode. Embodiments of the inventive concepts provide a voltage generator including an LDO regulator that supplies a first current to an internal voltage node of a sense amplification circuit as feedback control based on a voltage level of the internal voltage node; and a power switch circuit including a plurality of power switches each having one end connected to an external voltage and an opposite end connected to the internal voltage node, and that supplies a second current to the internal voltage node as feed-forward control based on a number of activated sense amplifiers of the sense amplification circuit. Embodiments of the inventive concepts further provide a memory device including a memory cell array including a plurality of memory cells; a sense amplification circuit that reads out data stored in the memory cell array; and an internal voltage generator that provides an internal voltage to the sense amplification circuit. The internal voltage generator compensates for a current consumed by the sense amplification circuit by respectively using feedback control and feed-forward control according to an operation mode of the sense amplification circuit. Embodiments of the inventive concepts still further provide a load block; and an internal voltage generator that provides a current consumed by the load block. The internal voltage generator compensates for the current consumed by the load block by selectively using feedback control and feed-forward control according to an operation mode of the load block. BRIEF DESCRIPTION OF THE DRAWINGS The above and other objects and features of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings. FIG. 1 is a block diagram illustrating a memory device 1000A according to embodiments of the inventive concepts. FIG. 2 is a diagram illustrating a bit line voltage sensing operation of a sense amplification circuit 1500 shown in FIG. 1. FIG. 3 is a diagram illustrating an example of an internal voltage generator 1800 of FIG. 1. FIGS. 4A and 4B are diagrams illustrating an example of an operation of an internal voltage generator 1800A of FIG. 3 in an operation mode. FIG. 5 is a diagram of another example of internal voltage generator 1800 of FIG. 1. FIG. 6 illustrates a diagram of an example operation of an internal voltage generator 1800B of FIG. 5. FIG. 7 illustrates voltages of internal voltage generator 1800B described with respect to FIG. 6. FIG. 8 illustrates a diagram of an example of external voltage detector 1823 of FIG. 5. FIG. 9 illustrates a diagram of another example of external voltage detector 1823 of FIG. 5. FIG. 10 illustrates a diagram of mode selector 1824 of FIG. 5. FIG. 11 illustrates a diagram of an example operation of external voltage detector 1823 in FIG. 5. FIG. 12 illustrates a diagram of an example of an internal voltage generator 1800C according embodiments of the inventive concepts. FIG. 13 illustrates a diagram of an example of internal voltage generator 1800D according to embodiments of the inventive concepts. FIG. 14 illustrates a diagram including error corrector 1827 of FIG. 13. FIG. 15 illustrates a diagram of operation of error corrector 1827 of FIG. 14. FIG. 16 illustrates a diagram of an example of application processor 1000B according to embodiments of the inventive concepts. DETAILED DESCRIPTION Hereinafter, various embodiments will be described with refe