US-12626750-B2 - Memory core circuit having cell on periphery (CoP) structure and memory device including the same

US12626750B2US 12626750 B2US12626750 B2US 12626750B2US-12626750-B2

Abstract

A memory core circuit includes a memory cell array including sub cell arrays and a core control circuit including sub peripheral circuits under the sub cell arrays. The sub peripheral circuits are divided into first and second column edge regions and a central region. The central region is between the first column edge region and the second column edge region. A sense amplifier region including a plurality of bitline sense amplifiers are disposed in at least one of the first column edge region and the second column edge region. A wordline driver region including a plurality of sub wordline drivers is disposed in the central region. At least a portion of device peripheral circuits configured to control the memory core circuit is disposed in a rest region other than the sense amplifier region and the wordline driver region.

Inventors

Sanghoon Jung
Yeongwoo Kang
CHULKWON PARK
Jeongdon Ihm
Changsik YOO
Keonwoo Park
Youngseok Park
Hyunchul YOON

Assignees

SAMSUNG ELECTRONICS CO., LTD.

Dates

Publication Date: 20260512
Application Date: 20240709
Priority Date: 20231229

Claims (20)

1 . A memory core circuit comprising: a memory cell array comprising a plurality of sub cell arrays that are arranged in a first matrix comprising a plurality of array rows and a plurality of array columns; and a core control circuit comprising a plurality of sub peripheral circuits that are arranged in a second matrix comprising the plurality of array rows and the plurality of array columns, wherein each sub peripheral circuit is disposed under a corresponding sub cell array of the plurality of sub cell arrays, wherein each sub cell array comprises a plurality of memory cells respectively connected to a plurality of wordlines and a plurality of bitlines, the plurality of wordlines extend in a row direction and are arranged in a column direction, and the plurality of bitlines extend in the column direction and are arranged in the row direction, wherein each sub peripheral circuit is divided into a first column edge region, a second column edge region and a central region, the first column edge region and the second column edge region correspond to end portions of each sub peripheral circuit in the column direction, and the central region is between the first column edge region and the second column edge region, wherein a sense amplifier region comprising a plurality of bitline sense amplifiers that respectively sense voltages of the plurality of bitlines is in at least one of the first column edge region and the second column edge region, wherein a wordline driver region comprising a plurality of sub wordline drivers that respectively drive the plurality of wordlines is in the central region, and wherein at least a portion of device peripheral circuits configured to control the memory core circuit is in a rest region other than the sense amplifier region and the wordline driver region.
2 . The memory core circuit of claim 1 , further comprising: a plurality of column selection lines configured to transfer a plurality of column selection signals, wherein the plurality of column selection lines extend in the column direction and are arranged in the row direction, and wherein a column decoder configured to generate the plurality of column selection signals is distributed in rest regions of the plurality of sub peripheral circuits.
3 . The memory core circuit of claim 2 , wherein the column decoder comprises a plurality of decoder blocks corresponding to the plurality of array columns, and wherein a decoder block corresponding to each array column is distributed in the column direction in one or more rest regions of respective two or more sub peripheral circuits in each array column.
4 . The memory core circuit of claim 2 , wherein, with respect to each sub peripheral circuit of the plurality of sub peripheral circuits, the central region is divided into a first sub central region and a second sub central region in the row direction, one of the first sub central region and the second sub central region corresponds to the wordline driver region, and wherein, with respect to at least one sub peripheral circuit, the other one of the first sub central region and the second sub central region corresponds to a column decoder region comprising the column decoder.
5 . The memory core circuit of claim 4 , wherein, with respect to a first sub peripheral circuit and a second sub peripheral circuit that are adjacent to each other in the column direction, the first sub central region of the first sub peripheral circuit and the first sub central region of the second sub peripheral circuit correspond to the column decoder region.
6 . The memory core circuit of claim 5 , wherein the plurality of column selection lines comprises a first plurality of column selection lines and a second plurality of column selection lines, and wherein the column decoder region in the first sub peripheral circuit is connected to the first plurality of column selection lines via row conduction paths extending in the row direction, and the column decoder region in the second sub peripheral circuit is connected to the second plurality of column selection lines without a use of row conduction paths.
7 . The memory core circuit of claim 4 , wherein, with respect to a first sub peripheral circuit and a second sub peripheral circuit that are adjacent to each other in the column direction, the first sub central region of the first sub peripheral circuit corresponds to the column decoder region and the second sub central region of the second sub peripheral circuit corresponds to the column decoder region.
8 . The memory core circuit of claim 7 , wherein the column decoder region in the first sub peripheral circuit and the column decoder region in the sub peripheral circuit are connected to the plurality of column selection lines without row conduction paths extending in the row direction.
9 . The memory core circuit of claim 1 , wherein the plurality of sub peripheral circuits comprises a first sub peripheral circuit, a second sub peripheral circuit, a third sub peripheral circuit and a fourth sub peripheral circuit, wherein the first sub peripheral circuit and the second sub peripheral circuit are adjacent to each other in the row direction, the third sub peripheral circuit is adjacent to the first sub peripheral circuit in the column direction, and the fourth sub peripheral circuit is adjacent to the second sub peripheral circuit in the column direction and adjacent to the third sub peripheral circuit, and wherein the first through forth sub peripheral circuits have a structure symmetric in the row direction and symmetric in the column direction, such that four rest regions respectively in the first through fourth sub peripheral circuits are adjacent to each other to form one combined region.
10 . The memory core circuit of claim 9 , wherein, with respect to each sub peripheral circuit of the plurality of sub peripheral circuits, the central region is divided into a first sub central region and a second sub central region in the row direction, wherein, with respect to the first sub peripheral circuit, the first column edge region corresponds to the sense amplifier region and the first sub central region corresponds to the wordline driver region, wherein, with respect to the second sub peripheral circuit, the first column edge region corresponds to the sense amplifier region and the second sub central region corresponds to the wordline driver region, wherein, with respect to the third sub peripheral circuit, the second column edge region corresponds to the sense amplifier region and the first sub central region corresponds to the wordline driver region, and wherein, with respect to the fourth sub peripheral circuit, the second column edge region corresponds to the sense amplifier region and the second sub central region corresponds to the wordline driver region.
11 . The memory core circuit of claim 1 , wherein each sub peripheral circuit of the plurality of sub peripheral circuits comprises a first plurality of bitline sense amplifiers, wherein the first plurality of bitline sense amplifiers comprises 2 N bitline sense amplifiers, the first plurality of bitline sense amplifiers being connected to first 2 N bitlines among 4 N bitlines corresponding to each sub peripheral circuit where N is a natural number, wherein the 4 N bitlines comprise the first 2 N bitlines and second 2 N bitlines, wherein a first N bitline sense amplifiers among the first plurality of bitline sense amplifiers are in the first column edge region of each sub peripheral circuit and a second N bitline sense amplifiers among the first plurality of bitline sense amplifiers are in the second column edge region of each sub peripheral circuit, and wherein the second 2 N bitlines are connected, as complementary bitlines, to a second plurality of bitline sense amplifiers in two sub peripheral circuits adjacent to each sub peripheral circuit in the column direction.
12 . The memory core circuit of claim 1 , wherein each odd-numbered sub peripheral circuit among sub peripheral circuits arranged in the column direction in one array column does not include bitline sense amplifiers, and each even-numbered sub peripheral circuit among the sub peripheral circuits arranged in the column direction in the one array column includes 4 N bitline sense amplifiers that are connected to 4 N bitlines, each bitline of the 4 N bitlines corresponding to each respective even-numbered sub peripheral circuit of the one array column, where N is a natural number, such that a first 2 N bitline sense amplifiers among the 4 N bitline sense amplifiers are in the first column edge region of each even-numbered sub peripheral circuit and a second 2 N bitline sense amplifiers among the 4 N bitline sense amplifiers are in the second column edge region of each even-numbered sub peripheral circuit, and wherein each bit line of the 4 N bitlines corresponding to each respective odd-numbered sub peripheral circuit is connected, as a complementary bitline, to a bitline sense amplifier in two even-numbered sub peripheral circuits adjacent to the respective odd-numbered sub peripheral circuit.
13 . The memory core circuit of claim 1 , wherein each sub peripheral circuit of the plurality of sub peripheral circuits comprises a first plurality of bitline sense amplifiers, wherein the first plurality of bitline sense amplifiers comprises 2 N bitline sense amplifiers, the first plurality of bitline sense amplifiers being connected to first 2 N bitlines among 4 N bitlines wherein the 4 N bitlines comprise the first 2 N bitlines and second 2 N bitlines, and the 4 N bitlines correspond to each sub peripheral circuit where N is a natural number, such that all of the 2 N bitline sense amplifiers are disposed in the first column edge region of each sub peripheral circuit or all of the 2 N bitline sense amplifiers are disposed in the second column edge region of each sub peripheral circuit, and wherein the second 2 N bitlines are connected, as complementary bitlines, to a second plurality of bitline sense amplifiers in one sub peripheral circuit adjacent to each sub peripheral circuit in the column direction.
14 . The memory core circuit of claim 1 , wherein, with respect to a first sub peripheral circuit and a second sub peripheral circuit that are adjacent to each other in the row direction, the first sub peripheral circuit does not include the wordline driver region and the second sub peripheral circuit comprises the wordline driver region corresponding to the central region.
15 . The memory core circuit of claim 1 , wherein, with respect to a first sub peripheral circuit and a second sub peripheral circuit that are adjacent to each other in the column direction, the first sub peripheral circuit does not include the sense amplifier region and the second sub peripheral circuit includes a first sense amplifier region corresponding to the first column edge region and a second sense amplifier region corresponding to the second column edge region.
16 . The memory core circuit of claim 1 , wherein the wordline driver region of each sub peripheral circuit of the plurality of sub peripheral circuits comprises: a first wordline driver region connected to first wordlines disposed above the central region in a vertical direction respectively perpendicular to the row direction and the column direction; a second wordline driver region connected to second wordlines disposed above the first column edge region in the vertical direction; and a third wordline driver region connected to third wordlines disposed above the second column edge region in the vertical direction.
17 . The memory core circuit of claim 16 , further comprising: column conduction paths extending in the column direction to connect the second wordlines to first sub wordline drivers in the second wordline driver region and connect the third wordlines to second sub wordline drivers in the third wordline driver region.
18 . The memory core circuit of claim 1 , wherein each memory cell comprises: a vertical channel transistor; and a cell capacitor on the vertical channel transistor.
19 . A memory core circuit comprising: a memory cell array comprising a plurality of sub cell arrays that are arranged in a first matrix comprising a plurality of array rows and a plurality of array columns; and a core control circuit comprising a plurality of sub peripheral circuits that are arranged in a second matrix comprising the plurality of array rows and the plurality of array columns, wherein each sub peripheral circuit is disposed under a corresponding sub cell array of the plurality of sub cell arrays, wherein each sub cell array comprises a plurality of dynamic random access memory (DRAM) cells respectively connected to a plurality of wordlines and a plurality of bitlines, the plurality of wordlines extend in a row direction and are arranged in a column direction, and the plurality of bitlines extend in the column direction and are arranged in the row direction, wherein each sub peripheral circuit of the plurality of sub peripheral circuits is divided into a first column edge region, a second column edge region and a central region, the first column edge region and the second column edge region correspond to both end portions of each sub peripheral circuit in the column direction, and the central region is between the first column edge region and the second column edge region, wherein a sense amplifier region comprising a plurality of bitline sense amplifiers that respectively sense voltages of the plurality of bitlines is in at least one of the first column edge region and the second column edge region, wherein a wordline driver region comprising a plurality of sub wordline drivers that respectively drive the plurality of wordlines is in the central region, and wherein a column decoder configured to generate a plurality of column selection signals is in a rest region other than the sense amplifier region and the wordline driver region.
20 . A memory device comprising: a memory core circuit; and device peripheral circuits configured to control the memory core circuit, the memory core circuit comprising: a memory cell array comprising a plurality of sub cell arrays that are arranged in a first matrix comprising a plurality of array rows and a plurality of array columns; and a core control circuit comprising a plurality of sub peripheral circuits that are arranged in a second matrix comprising the plurality of array rows and the plurality of array columns, wherein each sub peripheral circuit is disposed under a corresponding sub cell array of the plurality of sub cell arrays, wherein each sub cell array comprises a plurality of memory cells respectively connected to a plurality of wordlines and a plurality of bitlines, wherein the plurality of wordlines extend in a row direction and are arranged in a column direction, and the plurality of bitlines extend in the column direction and are arranged in the row direction, wherein each sub peripheral circuit of the plurality of sub peripheral circuits is divided into a first column edge region, a second column edge region and a central region, the first column edge region and the second column edge region correspond to both end portions of each sub peripheral circuit in the column direction, and the central region is between the first column edge region and the second column edge region, wherein a sense amplifier region comprising a plurality of bitline sense amplifiers that respectively sense voltages of the plurality of bitlines is in at least one of the first column edge region and the second column edge region, wherein a wordline driver region comprising a plurality of sub wordline drivers that respectively drive the plurality of wordlines is in the central region, and wherein at least a portion of device peripheral circuits configured to control the memory core circuit is in a rest region other than the sense amplifier region and the wordline driver region.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2023-0196940, filed on Dec. 29, 2023, in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference herein in its entirety. BACKGROUND 1. Field Example embodiments relate generally to semiconductor integrated circuits, and more particularly, to a memory core circuit having cell on periphery (CoP) structure and a memory device including the memory core circuit. 2. Description of Related Art As high-performance electronic products are desired to be miniaturized and multifunctional, a high degree of integration may be implemented to provide a high-capacity integrated circuit device. As the feature size of a memory device such as a dynamic random access memory (DRAM) device decreases, efficient arrangement of circuits for driving the memory device may be used. In the related art, a DRAM device has an open bitline structure, in which two bitlines forming a complementary pair exist on different cell blocks, and two bitlines are spread on both sides of the bitline sense amplifier. According to the limitations of characteristic implementation of the cell transistor of the conventional DRAM device and the increase in implementation difficulty, research is currently being conducted to implement the cell transistor with a vertical channel transistor (VCT) to reduce the size of the DRAM device. Even if a vertical structure is employed to reduce the size of the memory device, the size reduction of the memory device may be limited due to circuits for driving the memory cell array. SUMMARY Some example embodiments may provide a memory core circuit and a memory device including the memory core circuit, capable of efficiently disposing a core control circuit configured to drive a memory cell array. According to an aspect of the disclosure, a memory core circuit includes a memory cell array comprising a plurality of sub cell arrays that are arranged in a first matrix comprising a plurality of array rows and a plurality of array columns; and a core control circuit comprising a plurality of sub peripheral circuits that are arranged in a second matrix comprising the plurality of array rows and the plurality of array columns, wherein each sub peripheral circuit is under a corresponding sub cell array of the plurality of sub cell arrays, wherein each sub cell array comprises a plurality of memory cells respectively connected to a plurality of wordlines and a plurality of bitlines, wherein the plurality of wordlines extend in a row direction and is arranged in a column direction, wherein the plurality of bitlines extend in the column direction and are arranged in the row direction, wherein each sub peripheral circuit is divided into a first column edge region, a second column edge region and a central region, the first column edge region and the second column edge region correspond to both end portions of each sub peripheral circuit in the column direction, and the central region is between the first column edge region and the second column edge region, wherein a sense amplifier region comprising a plurality of bitline sense amplifiers that respectively sense voltages of the plurality of bitlines is in at least one of the first column edge region and the second column edge region, wherein a wordline driver region comprising a plurality of sub wordline drivers that respectively drive the plurality of wordlines is in the central region, and wherein at least a portion of device peripheral circuits configured to control the memory core circuit is in a rest region other than the sense amplifier region and the wordline driver region. According to an aspect of the disclosure, a memory core circuit includes a memory cell array comprising a plurality of sub cell arrays that are arranged in a first matrix comprising a plurality of array rows and a plurality of array columns; and a core control circuit comprising a plurality of sub peripheral circuits that are arranged in a second matrix comprising the plurality of array rows and the plurality of array columns, wherein each sub peripheral circuit is under a corresponding sub cell array of the plurality of sub cell arrays, wherein each sub cell array comprises: a plurality of dynamic random access memory (DRAM) cells respectively connected to a plurality of wordlines and a plurality of bitlines, wherein the plurality of wordlines extend in a row direction and is arranged in a column direction, wherein the plurality of bitlines extend in the column direction and are arranged in the row direction, wherein each sub peripheral circuit of the plurality of sub peripheral circuits is divided into a first column edge region, a second column edge region and a central region, the first column edge region and the second column edge region correspond to both end portions of each sub peripheral circuit in the column direction, and the central