US-12626751-B2 - Microelectronic devices, and related memory devices and electronic systems

US12626751B2US 12626751 B2US12626751 B2US 12626751B2US-12626751-B2

Abstract

A microelectronic device includes a memory array structure and a control circuitry structure vertically overlying and bonded to the memory array structure. The memory array structure includes array regions respectively including memory cells, digit lines, and word lines within horizontal areas thereof. The control circuitry structure includes control circuitry regions, sense amplifier (SA) sections including SA circuitry, and sub-word line driver (SWD) sections including SWD circuitry. The control circuitry regions horizontally overlap the array regions of the memory array structure. The SA sections respectively horizontally overlap each of two of the control circuitry regions horizontally neighboring one another in a first direction. The SWD sections are respectively interposed between two other of the control circuitry regions horizontally neighboring one another in a second direction orthogonal to the first direction. Additional microelectronic devices, memory devices, and electronic systems are also described.

Inventors

Fatma Arzum Simsek-Ege
Beau D. Barry

Assignees

MICRON TECHNOLOGY, INC.

Dates

Publication Date: 20260512
Application Date: 20240110

Claims (20)

1 . A microelectronic device, comprising: a memory array structure comprising array regions respectively comprising memory cells, digit lines, and word lines within horizontal areas thereof; and a control circuitry structure vertically overlying and bonded to the memory array structure, the control circuitry structure comprising: control circuitry regions horizontally overlapping the array regions of the memory array structure; sense amplifier (SA) sections comprising SA circuitry, the SA sections respectively horizontally overlapping each of two of the control circuitry regions horizontally neighboring one another in a first direction; and sub-word line driver (SWD) sections comprising SWD circuitry, the SWD sections respectively interposed between two other of the control circuitry regions horizontally neighboring one another in a second direction orthogonal to the first direction.
2 . The microelectronic device of claim 1 , wherein the memory array structure further comprises: digit line exit regions alternating with the array regions in the first direction and respectively comprising: end portions of some of the digit lines; and digit line contacts coupled to the end portions of the some of the digit lines; and word line exit regions alternating with the array regions in the second direction and respectively comprising: end portions of some of the word lines; and word line contacts coupled to the end portions of the some of the word lines.
3 . The microelectronic device of claim 2 , wherein the control circuitry structure further comprises: digit line contact regions alternating with the control circuitry regions in the first direction and respectively comprising: additional digit line contacts coupled to the digit line contacts within a respective one of the digit line exit regions of the memory array structure; and routing structures coupled to the additional digit line contacts and to the SA circuitry of a respective one of the SA sections; and word line contact regions alternating with the control circuitry regions in the second direction and respectively comprising: additional word line contacts coupled to the word line contacts within a respective one of the word line exit regions of the memory array structure; and additional routing structures coupled to the additional word line contacts and to the SWD circuitry of a respective one of the SWD sections.
4 . The microelectronic device of claim 3 , wherein: the digit line contact regions of the control circuitry structure horizontally overlap the digit line exit regions of the memory array structure; and the word line contact regions of the control circuitry structure horizontally overlap the word line exit regions of the memory array structure.
5 . The microelectronic device of claim 4 , wherein horizontal areas of the digit line contact regions of the control circuitry structure are greater than horizontal areas of the digit line exit regions of the memory array structure.
6 . The microelectronic device of claim 4 , wherein the additional digit line contacts within the digit line contact regions of the control circuitry structure physically contact the digit line contacts within the digit line exit regions of the memory array structure.
7 . The microelectronic device of claim 3 , wherein the SA sections of the control circuitry structure respectively horizontally overlap one of the digit line contact regions horizontally interposed in the first direction between the two of the control circuitry regions.
8 . The microelectronic device of claim 3 , wherein the SWD sections of the control circuitry structure are substantially confined within horizontal areas of word line exit regions of the memory array structure.
9 . The microelectronic device of claim 3 , wherein the digit line contact regions of the control circuitry structure comprise horizontally adjacent read/write (RW) gap areas of horizontally neighboring SA devices of the SA sections.
10 . The microelectronic device of claim 1 , wherein the control circuitry structure further comprises mini-gap (MG) sections respectively interposed between two of the SA sections horizontally neighboring one another in the second direction and two of the SWD sections horizontally neighboring one another in the first direction, the MG sections comprising routing structures operatively associated with the SA circuitry and the SWD circuitry.
11 . A memory device, comprising: a memory array structure comprising: array regions comprising memory cells, digit lines, and word lines; digit line exit regions horizontally alternating with the array regions in a first direction and comprising horizontal ends of the digit lines within horizontal areas thereof; and word line exit regions horizontally alternating with the array regions in a second direction and comprising horizontal ends of the word lines within horizontal areas thereof; a control circuitry structure vertically overlying and bonded to the memory array structure, the control circuitry structure comprising: control circuitry regions horizontally overlapping the array regions of the memory array structure; sense amplifier (SA) sections comprising SA devices, the SA sections respectively horizontally overlapping two of the control circuitry regions neighboring one another in the first direction; digit line contact regions within horizontal areas of the SA sections and horizontally overlapping the digit line exit regions of the memory array structure, horizontal areas of the digit line contact regions defined by horizontally adjacent read/write (RW) gap areas of pairs of the SA devices of the SA sections; sub-word line driver (SWD) sections comprising SWD devices, the SWD sections respectively horizontally interposed between two other of the control circuitry regions neighboring one another in the second direction; and word line contact regions within horizontal areas of the SWD sections and horizontally overlapping the word line exit regions of the memory array structure.
12 . The memory device of claim 11 , wherein the SA devices of the SA sections comprise voltage transfer characteristic (VTC) SA devices, each of the VTC SA devices comprising: a RW gap area; an N-type sense amplifier (NSA) area neighboring the RW gap area and including NSA circuitry; a VTC area neighboring the NSA area and including VTC circuitry; a P-type sense amplifier (PSA) area neighboring the VTC area and including PSA circuitry; an additional VTC area neighboring the PSA area and including additional VTC circuitry; an additional NSA area neighboring the additional VTC area and including additional NSA circuitry; and a column select (CS) area neighboring the additional NSA area and including CS circuitry.
13 . The memory device of claim 11 , wherein: the digit lines of the memory array structure comprise: odd digit lines; and even digit lines horizontally alternating with the odd digit lines in the second direction; and the SA sections of the control circuitry structure comprise: odd SA sections comprising odd SA devices coupled to the odd digit lines; and even SA sections horizontally alternating with the odd SA sections in the first direction and comprising even SA devices coupled to the even digit lines.
14 . The memory device of claim 13 , wherein the digit line contact regions of the control circuitry structure comprise: odd digit line contact regions within horizontal areas of the odd SA sections and comprising: odd digit line contacts coupled to the odd digit lines; and odd digit line routing structures extending between and coupled to the odd digit line contacts and the odd SA devices of the odd SA sections; and even digit line contact regions within horizontal areas of the even SA sections and comprising: even digit line contacts coupled to the even digit lines; and even digit line routing structures extending between and coupled to the even digit line contacts and the even SA devices of the even SA sections.
15 . The memory device of claim 11 , wherein: the word lines of the memory array structure comprise: odd word lines; and even word lines alternating with the odd word lines in the first direction; and the SWD sections of the control circuitry structure comprise: odd SWD sections comprising odd SWD devices coupled to the odd word lines; and even SWD sections horizontally alternating with the odd SWD sections in the second direction and comprising even SWD devices coupled to the even word lines.
16 . The memory device of claim 15 , wherein the word line contact regions of the control circuitry structure comprise: odd word line contact regions within horizontal areas of the odd SWD sections and comprising: odd word line contacts coupled to the odd word lines; and odd word line routing structures extending between and coupled to the odd word line contacts and the odd SWD devices of the odd SWD sections; and even word line contact regions within horizontal areas of the even SWD sections and comprising: even word line contacts coupled to the even word lines; and even word line routing structures extending between and coupled to the even word line contacts and the even SWD devices of the even SWD sections.
17 . The memory device of claim 11 , wherein each of the SWD sections of the control circuitry structure is substantially confined within a horizontal area of a respective one of the word line exit regions of the memory array structure.
18 . The memory device of claim 11 , wherein the control circuitry structure further comprises mini-gap (MG) sections respectively extending in the first direction between a horizontally neighboring pair of the SWD sections and respectively extending in the second direction between a horizontally neighboring pair of the SA sections, the MG sections respectively comprising: conductive routing structures coupled to at least some of the SWD devices of the horizontally neighboring pair of the SWD sections; and additional conductive routing structures coupled to at least some of the SA devices of the horizontally neighboring pair of the SA sections.
19 . An electronic system, comprising: a processor device operably connected to an input device and an output device; and a memory device operably connected to the processor device and comprising: a memory array structure comprising array regions respectively comprising memory cells, digit lines, and word lines within horizontal areas thereof; and a control circuitry structure vertically overlying and bonded to the memory array structure, the control circuitry structure comprising: control circuitry regions horizontally overlapping the array regions of the memory array structure; sense amplifier (SA) sections comprising SA circuitry, the SA sections respectively overlapping two of the control circuitry regions neighboring one another in a first horizontal direction; digit line contact regions within horizontal areas of the SA sections and comprising conductive structures coupled to the SA circuitry and the digit lines; sub-word line driver (SWD) sections comprising SWD circuitry, the SWD sections respectively interposed between two other of the control circuitry regions neighboring one another in a second horizontal direction orthogonal to the first horizontal direction; and word line contact regions within horizontal areas of the SWD sections and comprising additional conductive structures coupled to the SWD circuitry and the word lines.
20 . The electronic system of claim 19 , wherein the memory cells comprise dynamic random access memory (DRAM) cells.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application claims the benefit under 35 U.S.C. § 119(e) of U.S. Provisional Patent Application Ser. No. 63/486,778, filed Feb. 24, 2023, the disclosure of which is hereby incorporated herein in its entirety by this reference. TECHNICAL FIELD The disclosure, in various embodiments, relates generally to the field of microelectronic device design and fabrication. More specifically, the disclosure relates to microelectronic devices including a control circuitry structure overlying a memory array structure, and to related memory devices and electronic systems. BACKGROUND Microelectronic device designers often desire to increase the level of integration or density of features within a microelectronic device by reducing the dimensions of the individual features and by reducing the separation distance between neighboring features. In addition, microelectronic device designers often desire to design architectures that are not only compact, but offer performance advantages, as well as simplified, easier and less expensive to fabricate designs. One example of a microelectronic device is a memory device. Memory devices are generally provided as internal integrated circuits in computers or other electronic devices. There are many types of memory devices including, but not limited to, volatile memory devices. One type of volatile memory device is a dynamic random access memory (DRAM) device. A DRAM device may include a memory array including DRAM cells arranged in rows extending in a first horizontal direction and columns extending in a second horizontal direction. In one design configuration, an individual DRAM cell includes an access device (e.g., a transistor) and a storage node device (e.g., a capacitor) electrically connected to the access device. The DRAM cells of a DRAM device are electrically accessible through digit lines and word lines arranged along the rows and columns of the memory array and in electrical communication with control logic devices within a base control logic structure of the DRAM device. Control logic devices within a base control logic structure underlying a memory array of a DRAM device have been used to control operations on the DRAM cells of the DRAM device. Control logic devices of the base control logic structure can be provided in electrical communication with digit lines and word lines coupled to the DRAM cells by way of routing and contact structures. Unfortunately, the quantities, dimensions, and arrangements of the different control logic devices employed within the base control logic structure can also undesirably impede reductions to the size (e.g., horizontal footprint) of a memory device, and/or improvements in the performance (e.g., faster memory cell ON/OFF speed, lower threshold switching voltage requirements, faster data transfer rates, lower power consumption) of the DRAM device. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a simplified, partial longitudinal cross-sectional view of a microelectronic device, in accordance with embodiments of the disclosure. FIG. 2 is a simplified, schematic view of a memory array structure for the microelectronic device depicted in FIG. 1, in accordance with some embodiments of the disclosure. FIG. 3 is a simplified, expanded schematic view of a portion of the memory array structure depicted in FIG. 2, in accordance with some embodiments of the disclosure. FIG. 4 is a simplified, schematic view of a control circuitry structure for the microelectronic device depicted in FIG. 1, in accordance with some embodiments of the disclosure. FIG. 5 is a simplified, expanded schematic view of a portion of the control circuitry structure depicted in FIG. 4, in accordance with some embodiments of the disclosure. FIG. 6 is a simplified, partial longitudinal cross-sectional view of the microelectronic device depicted in FIG. 1, including features of the memory array structure depicted in FIG. 2 and the control circuitry structure depicted in FIG. 4, in accordance with some embodiments of the disclosure. FIG. 7 is a simplified, schematic block diagram of an electronic system, in accordance with some embodiments of the disclosure. DETAILED DESCRIPTION The following description provides specific details, such as material compositions, shapes, and sizes, in order to provide a thorough description of embodiments of the disclosure. However, a person of ordinary skill in the art would understand that the embodiments of the disclosure may be practiced without employing these specific details. Indeed, the embodiments of the disclosure may be practiced in conjunction with conventional microelectronic device fabrication techniques employed in the industry. In addition, the description provided below does not form a complete process flow for manufacturing a microelectronic device (e.g., a memory device). The structures described below do not form a complete microelectronic device. Only those process acts and structures necessa