US-12626753-B2 - Wafer-on-wafer formed memory and logic

Abstract

A wafer-on-wafer formed memory and logic device can enable high bandwidth transmission of data directly between a memory die and a logic die. The memory die can be formed as one of many memory dies on a first semiconductor wafer. The logic die can be formed as one of many logic dies on a second semiconductor wafer. The first and second wafers can be bonded via a wafer-on-wafer bonding process. The memory and logic device can be singulated from the bonded first and second wafers.

Inventors

• Sean S. Eilert
• Aliasger T. Zaidy
• Glen E. Hush
• Kunal R. Parekh

Assignees

• MICRON TECHNOLOGY, INC.

Dates

Publication Date

20260512

Application Date

20220809

Claims (4)

1. 1 . An apparatus, comprising: a memory device formed on a memory die, the memory device comprising: an array of memory cells; and memory-to-logic circuitry coupled to the array of memory cells; a logic device formed on a logic die, the logic device comprising: logic circuitry; and logic-to-memory circuitry coupled to the logic circuitry; and a bond formed between the memory die and the logic die via a wafer-on-wafer bonding process; wherein the memory-to-logic circuitry is configured to transmit signals indicative of data between the array of memory cells and the logic-to-memory circuitry via the bond; wherein the logic-to-memory circuitry is configured to transmit signals indicative of data between the logic circuitry and the memory-to-logic circuitry via the bond; and wherein the logic circuitry comprises one of: an artificial intelligence accelerator; a communication circuit from a group of communication circuits including a radio frequency communication circuit and a 5G communication circuit; a sensor circuit from a group of sensor circuits including a video circuit, an imaging circuit, a radar circuit, and a smart sensor circuit; and a network circuit from a group of network circuits including a packet routing circuit and an intrusion-detection circuit.
2. 2 . The apparatus of claim 1 , wherein the bond is formed via the wafer-on-wafer bonding process between a first wafer including the memory device formed on the memory die and a second wafer including the logic device formed on the logic die; and wherein the apparatus is singulated from the bonded first and second wafers.
3. 3 . The apparatus of claim 1 , wherein the memory device further comprises: a host interface coupled to the array of memory cells; and a transceiver coupled to the host interface and to the memory-to-logic circuitry; wherein the transceiver is configured to select a data output path for the memory array between the host interface and the memory-to-logic circuitry.
4. 4 . The apparatus of claim 1 , wherein the memory device further comprises a host interface coupled to the array of memory cells; wherein the logic device further comprises a transceiver coupled to the logic-to-memory circuitry and to the logic circuitry; and wherein the transceiver is configured to select a data output path for the memory array between the host interface and the memory-to-logic circuitry.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority to U.S. Provisional Application 63/231,660, filed Aug. 10, 2021, which is incorporated by reference. TECHNICAL FIELD The present disclosure relates generally to memory, and more particularly to apparatuses and methods associated with wafer-on-wafer memory and logic. BACKGROUND Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic devices. There are many different types of memory including volatile and non-volatile memory. Volatile memory can require power to maintain its data and includes random-access memory (RAM), dynamic random access memory (DRAM), and synchronous dynamic random access memory (SDRAM), among others. Non-volatile memory can provide persistent data by retaining stored data when not powered and can include NAND flash memory, NOR flash memory, read only memory (ROM), Electrically Erasable Programmable ROM (EEPROM), Erasable Programmable ROM (EPROM), and resistance variable memory such as phase change random access memory (PCRAM), resistive random access memory (RRAM), and magnetoresistive random access memory (MRAM), among others. Memory is also utilized as volatile and non-volatile data storage for a wide range of electronic applications. including, but not limited to personal computers, portable memory sticks, digital cameras, cellular telephones, portable music players such as MP3 players, movie players, and other electronic devices. Memory cells can be arranged into arrays, with the arrays being used in memory devices. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of an apparatus in the form of a system including a memory device and a logic device. FIG. 2A is a top view of a memory wafer in accordance with a number of embodiments of the present disclosure. FIG. 2B is a top view of a logic wafer in accordance with a number of embodiments of the present disclosure. FIG. 2C is a cross-section of a portion of the memory wafer bonded to the logic wafer in accordance with a number of embodiments of the present disclosure. FIG. 2D illustrates a portion of the bonded wafers including a memory die and a logic die after dicing in accordance with a number of embodiments of the present disclosure. FIG. 3A illustrates a circuit diagram of a memory die in accordance with a number of embodiments of the present disclosure. FIG. 3B illustrates a circuit diagram of a memory bank group in accordance with a number of embodiments of the present disclosure. FIG. 3C illustrates a memory bank in accordance with a number of embodiments of the present disclosure. FIG. 3D illustrates a memory bank in accordance with a number of embodiments of the present disclosure. FIG. 3E illustrates a memory tile in accordance with a number of embodiments of the present disclosure. FIG. 3F illustrates a portion of a memory tile in accordance with a number of embodiments of the present disclosure. FIG. 3G illustrates a portion of a memory tile in accordance with a number of embodiments of the present disclosure. FIG. 4A is a block diagram of an example of a memory-logic architecture in accordance with a number of embodiments of the present disclosure. FIG. 4B is a block diagram of a first portion of the architecture illustrated in FIG. 4A. FIG. 4C is a block diagram of a second portion of the architecture illustrated in FIG. 4A. DETAILED DESCRIPTION The present disclosure includes apparatuses and methods related to wafer-on-wafer formed memory and logic. Inexpensive and energy-efficient logic devices have been proposed. Such devices can benefit from being tightly coupled to memory devices. Logic devices can be artificial intelligence (AI) accelerators such as deep learning accelerators (DLAs). AI refers to the ability to improve a machine through “learning” such as by storing patterns and/or examples which can be utilized to take actions at a later time. Deep learning refers to a device's ability to learn from data provided as examples. Deep learning can be a subset of AI. Neural networks, among other types of networks, can be classified as deep learning. The low power, inexpensive design of deep learning accelerators can be implemented in internet-of-things (IOT) devices. The DLAs can process and make intelligent decisions at run-time. Memory devices including the edge DLAs can also be deployed in remote locations without cloud or offloading capability. A three-dimensional integrated circuit (3D IC) is a metal-oxide semiconductor (MOS) IC manufactured by stacking semiconductor wafers or dies and interconnecting them vertically using, for example, through-silicon vias (TSVs) or metal connections, to function as a single device to achieve performance improvements at reduced power and smaller footprint than conventional two-dimensional processes. Examples of 3D ICs include hybrid memory cube (HMC) and high bandwidth memory (HBM), among others. Methods for manufacturing 3D ICs inclu