US-12626754-B2 - Semiconductor device having pad electrode equipped with low pass filter circuit

Abstract

An example apparatus includes a passgate circuit between first and second nodes, the passgate circuit having a plurality of transistors at least two of which are operatively connected in parallel in a first mode and operatively connected in series in a second mode. The plurality of transistors may include first and second transistors coupled in parallel between the first and second nodes and controlled in common by a first control signal activated in the first mode. The plurality of transistors may further include third and fourth transistors connected in series between the first and second nodes and controlled in common by a second control signal activated in the second mode.

Inventors

• Nobuki Takahashi
• Kohei Nakamura

Assignees

• MICRON TECHNOLOGY, INC.

Dates

Publication Date

20260512

Application Date

20240415

Claims (18)

1. 1 . An apparatus comprising a passgate circuit between first and second nodes, the passgate circuit having a plurality of transistors at least two of which are operatively connected in parallel in a first mode and operatively connected in series in a second mode, wherein the first node is coupled to a pad electrode supplied with a signal from outside; and an ODT circuit coupled to the pad electrode and deactivated in the second mode.
2. 2 . The apparatus of claim 1 , wherein the second node is coupled to an input node of an input buffer circuit.
3. 3 . The apparatus of claim 1 , wherein the plurality of transistors includes first and second transistors coupled in parallel between the first and second nodes and controlled in common by a first control signal activated in the first mode.
4. 4 . The apparatus of claim 3 , wherein the plurality of transistors further includes third and fourth transistors coupled in series between the first and second nodes and controlled in common by a second control signal activated in the second mode.
5. 5 . The apparatus of claim 4 , wherein the second control signal is activated in each of the first and second modes.
6. 6 . The apparatus of claim 5 , wherein the first control signal is deactivated in the second mode.
7. 7 . The apparatus of claim 4 , wherein the second control signal is deactivated in the first mode.
8. 8 . The apparatus of claim 1 , wherein the plurality of transistors includes first and second transistors coupled in parallel between the first and second nodes, wherein the first transistor is controlled by a first control signal, and wherein the second transistor is controlled by a second control signal different from the first control signal.
9. 9 . The apparatus of claim 1 , wherein the passgate circuit further has a capacitor, wherein the plurality of transistors includes a first transistor coupled between the first node and the capacitor.
10. 10 . An apparatus comprising: an internal pad electrode; an input buffer circuit; an ODT circuit coupled to the internal pad electrode; and a passgate circuit including first and second signal paths operatively connected between the internal pad electrode and the input buffer circuit in parallel, wherein the first and second signal paths are different in resistance value from each other, wherein the first signal path is electrically connected between the internal pad electrode and the input buffer when a first control signal is activated and is electrically disconnected between the internal pad electrode and the input buffer when the first control signal is deactivated, and wherein the ODT circuit is deactivated when the first control signal is deactivated.
11. 11 . The apparatus of claim 10 , wherein the second signal path is electrically connected between the internal pad electrode and the input buffer when a second control signal is activated.
12. 12 . The apparatus of claim 10 , wherein the first signal path is lower in resistance value than the second signal path.
13. 13 . The apparatus of claim 12 , wherein the first signal path includes a first plurality of transistors coupled between the internal pad electrode and the input buffer circuit in parallel.
14. 14 . The apparatus of claim 13 , wherein the second signal path includes a second plurality of transistors coupled between the internal pad electrode and the input buffer circuit in series.
15. 15 . The apparatus of claim 10 , further comprising an external pad electrode supplied with a command/address signal from outside, wherein the external pad electrode and the internal pad electrode are electrically connected via an iRDL.
16. 16 . An apparatus comprising: a pad electrode; an input buffer circuit; an ODT circuit coupled to the pad electrode; and a passgate circuit including a first plurality of transistors coupled in parallel between the pad electrode and the input buffer circuit and a second plurality of transistors coupled in series between the pad electrode and the input buffer circuit, wherein the first plurality of transistors are brought into an ON state in a first mode, and wherein the second plurality of transistors are brought into an ON state and the ODT circuit is deactivated in a second mode.
17. 17 . The apparatus of claim 16 , wherein the second plurality of transistors are brought into an ON state in each of the first and second modes.
18. 18 . An apparatus comprising a passgate circuit between first and second nodes, the passgate circuit having a plurality of transistors at least two of which are operatively connected in parallel in a first mode and operatively connected in series in a second mode, wherein the plurality of transistors includes first and second transistors coupled in parallel between the first and second nodes and controlled in common by a first control signal activated in the first mode, wherein the plurality of transistors further includes third and fourth transistors coupled in series between the first and second nodes and controlled in common by a second control signal activated in the second mode, and wherein the second control signal is deactivated in the first mode.

Description

CROSS-REFERENCE TO RELATED APPLICATION(S) This application claims priority to U.S. Provisional Application No. 63/502,989, filed May 18, 2023. The aforementioned application is incorporated herein by reference, in its entirety, for any purpose. BACKGROUND A semiconductor device such as a DRAM (Dynamic Random Access Memory) may have a high-speed operation mode and a low-speed operation mode. Since frequencies of signals input to a semiconductor device from outside are different in a high-speed operation mode and a low-speed operation mode, if the semiconductor device is designed such that circuit characteristics of an input circuit are optimized for a high-speed operation mode, the signal quality of signals input to the semiconductor device may be degraded in a low-speed operation mode. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram explaining a configuration of a semiconductor device according to an embodiment of the present disclosure. FIG. 2 is a block diagram explaining an internal configuration of a DRAM chip. FIG. 3 is an example of signal waveforms of a command/address signal on an internal pad electrode. FIG. 4 is a circuit diagram of a passgate circuit. FIGS. 5A to 5C are explanatory diagrams of an operation mode of the passgate circuit. FIGS. 6 to 8 are circuit diagrams of passgate circuits according to modifications. DETAILED DESCRIPTION Various embodiments of the present disclosure will be explained below in detail with reference to the accompanying drawings. The following detailed description refers to the accompanying drawings that show, by way of illustration, specific aspects, and various embodiments of the present disclosure. The detailed description provides sufficient detail to enable those skilled in the art to practice these embodiments of the present disclosure. Other embodiments may be utilized, and structural, logical, and electrical changes may be made without departing from the scope of the present disclosure. The various embodiments disclosed herein are not necessary mutually exclusive, as some disclosed embodiments can be combined with one or more other disclosed embodiments to form new embodiments. FIG. 1 is a block diagram explaining a configuration of a semiconductor device according to an embodiment of the present disclosure. As shown in FIG. 1, a semiconductor device 10 according to the present embodiment is a DRAM. The semiconductor device 10 is constituted of a DRAM chip 11 including an internal pad electrode 13 and a DRAM package 12 including an external pad electrode 14. The internal pad electrode 13 and the external pad electrode 14 are connected to each other via the DRAM package 12. The DRAM package 12 and the internal pad electrode 13 are positioned on the topmost wiring layer of the DRAM chip 11 and are connected to each other via an iRDL (inline redistribution layer) 15 formed on a wiring layer on which the internal pad electrode 13 is provided. The external pad electrode 14 is connected to an SoC (system-on-chip) 17 via an SoC package 16. Signals output from the SoC 17 are supplied to the internal pad electrode 13 on the DRAM chip 11 via the external pad electrode 14 and the iRDL 15. FIG. 2 is a block diagram explaining an internal configuration of the DRAM chip 11. As shown in FIG. 2, the DRAM chip 11 includes a memory cell array 20 having a plurality of DRAM cells and a control logic circuit 21 that controls the memory cell array 20. A command/address signal CA is supplied to the control logic circuit 21 from outside via the internal pad electrode 13. An ESD protection circuit 22, a CDM protection circuit 23, and an ODT circuit 24 are connected to the internal pad electrode 13. The command/address signal CA input to the internal pad electrode 13 is supplied to the control logic circuit 21 via a passgate circuit 25 and an input buffer circuit 26. Circuit characteristics of the ODT circuit 24 and the passgate circuit 25 are controlled by the control logic circuit 21. For example, when the semiconductor device 10 is set in a high-speed operation mode, by activating the ODT circuit 24, the internal pad electrode 13 is caused to function as a terminating resistor. Meanwhile, when the semiconductor device 10 is set in a low-speed operation mode, by deactivating the ODT circuit 24, the consumption current of the semiconductor device 10 is reduced. FIG. 3 is an example of signal waveforms of the command/address signal CA on the internal pad electrode 13 when the ODT circuit 24 is deactivated. As shown in FIG. 3, the command/address signal CA has a predetermined amplitude around a reference level Vref. However, when the ODT circuit 24 is deactivated, since the command/address signal CA input to the internal pad electrode 13 is reflected, ring-back indicated with the sign A may occur right after the command/address signal CA changes from a low level to a high level or right after the command/address signal CA changes from a high level to a low level. When such