US-12626755-B2 - Memory device having variable impedance memory cells and time-to-transition sensing of data stored therein

Abstract

The present disclosure relates to circuits, systems, and methods of operation for a memory device. In an example, a memory device includes a memory array including a plurality of memory cells, each memory cell having an impedance that varies in accordance with a respective data value stored therein; and a tracking memory cell having an impedance based on a tracking data value stored therein; and a read circuit coupled to the memory array, the read circuit configured to determine an impedance of a selected memory cells with respect to the impedance of the tracking memory cell; read a data value stored within the selected memory cell based upon a voltage change of a signal node voltage corresponding to the impedance of the selected memory cell.

Inventors

• Ravindraraj Ramaraju

Assignees

• R&D 3 LLC

Dates

Publication Date

20260512

Application Date

20231227

Claims (14)

1. 1 . A memory device, comprising: a plurality of memory cells, wherein each memory cell of the plurality of memory cells has a respective variable impedance that varies in accordance with a respective data value stored therein, and a read circuit configured to count a clock signal and generate a clock at one or more predetermined count values, and read, using the clock generated at the one or more predetermined count values, the data value stored within a selected memory cell based upon a variable time delay determination of a signal node voltage change corresponding to the respective variable impedance of the selected memory cell, wherein the read circuit comprises a plurality of registers configured to receive the clock generated at the one or more predetermined count values, wherein the plurality of registers comprise a first register and a second register that are connected serially, and wherein an output of the first register is configured to drive an input of the second register; and wherein the read circuit is configured to effect a change in voltage of the signal node at a variable rate corresponding to the variable impedance of the selected memory cell, and to read the data value stored within the selected memory cell based upon the variable time delay determination of the signal node voltage change.
2. 2 . The memory device of claim 1 , wherein the respective variable impedance comprises a respective variable current.
3. 3 . The memory device of claim 1 , wherein each respective data value corresponds to a plurality of bits.
4. 4 . The memory device of claim 3 , wherein the one or more predetermined count values correspond to the plurality of bits.
5. 5 . The memory device of claim 4 , wherein the plurality of memory cells comprises volatile memory cells.
6. 6 . The memory device of claim 4 , wherein the plurality of memory cells comprises non-volatile memory cells.
7. 7 . The memory device of claim 4 , wherein: each memory cell comprises multiple transistors whose respective gate voltage varies with the data written thereto, and the multiple transistors together determine the variable impedance of the memory cell.
8. 8 . The memory device of claim 1 , wherein the signal node comprises a read bit line node.
9. 9 . A method of reading a memory device, the method comprising: determining, using a read circuit of the memory device, a data value stored within a selected memory cell of a plurality of memory cells of the memory device, wherein: the read circuit comprises: a circuit configured to count a clock signal and generate a clock at one or more predetermined count values; a plurality of registers configured to receive the clock generated at the one or more predetermined count values, wherein the plurality of registers comprises a first register and a second register that are connected serially, and wherein an output of the first register is configured to drive an input of the second register; and a time-to-transition measurement circuit; wherein the determining the data value stored within the selected memory cell comprises: reading, using the clock generated at the one or more predetermined count values, a voltage transition of a signal node at a variable rate corresponding to the data value stored within the selected memory cell, and performing a time-to-transition measurement of the signal node, by the time-to-transition measurement circuit, to determine the data value stored within the selected memory cell.
10. 10 . The method of claim 9 , wherein each respective data value corresponds to a plurality of bits.
11. 11 . The method of claim 10 , wherein the one or more predetermined count values correspond to the plurality of bits.
12. 12 . The method of claim 9 , wherein the variable impedance of each memory cell arises from a transistor within the cell whose gate voltage varies with the data written thereto.
13. 13 . The method of claim 12 , wherein the plurality of memory cells comprises volatile memory cells.
14. 14 . The method of claim 9 , wherein an output of the read circuit is a value of a function operation performed on the selected memory cell.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS The present application is a continuation of U.S. application Ser. No. 18/046,142, titled “Memory Device Having Variable Impedance Memory Cells and Time-To-Transition Sensing of Data Stored Therein,” filed Oct. 12, 2022, which is a continuation of U.S. application Ser. No. 17/105,927, titled “Memory Device Having Variable Impedance Memory Cells and Time-To-Transition Sensing of Data Stored Therein,” filed Nov. 27, 2020, which is a continuation-in-part of U.S. application Ser. No. 16/802,902, titled “Memory Device Having Variable Impedance Memory Cells and Time-To-Transition Sensing of Data Stored Therein,” filed Feb. 27, 2020, which is a continuation of U.S. patent application Ser. No. 16/359,948, titled “Memory Device Having Variable Impedance Memory Cells and Time-To-Transition Sensing of Data Stored Therein,” filed Mar. 20, 2019 (now U.S. Pat. No. 10,629,256), which is a continuation of U.S. patent application Ser. No. 16/040,419, titled “Memory Device Having Variable Impedance Memory Cells and Time-To-Transition Sensing of Data Stored Therein,” filed Jul. 19, 2018 (now U.S. Pat. No. 10,269,413), which claims the benefit of U.S. Provisional Patent Application No. 62/650,067, filed Mar. 29, 2018, titled “Memory Structures and Related Methods of Operation,” and further claims the benefit of U.S. Provisional Patent Application No. 62/573,460, filed Oct. 17, 2017, titled “Memory Operation.” All applications are incorporated herein by reference in their entirety. TECHNICAL FIELD The present disclosure relates to circuits, systems, and methods of operation for a memory device, and more particularly relates to devices whose memory cells have a variable impedance that varies in accordance with a respective data value stored therein. BACKGROUND Memory may be used for many different types of purposes in a computing system. For example, memory may be used to store data or perform mathematical operations. Different types of memory may be used for these various purposes. Dynamic random-access memory (DRAM) may be used in situations that benefit from low-cost and high-capacity memory, and may be used in main memory components of a computing system. DRAM may be slower than other kinds of memory such as static random-access memory (SRAM). SUMMARY Memory devices are disclosed that generally perform a time delay determination of a voltage change on a signal node to determine the data value stored within a selected memory cell. In one disclosed embodiment, a memory device includes a plurality of memory cells, each memory cell having a variable impedance that varies in accordance with a respective data value stored therein. The memory device also includes a read circuit configured to read the data value stored within a selected memory cell based upon a variable time delay determination of a signal node voltage change corresponding to the variable impedance of the selected memory cell. In another disclosed embodiment, a memory device includes a plurality of memory cells in an array, and a read circuit. The read circuit is configured to effect a voltage transition of a signal node at a variable rate corresponding to a data value stored within a selected memory cell, and to perform a time-to-transition measurement of the signal node to determine the data value stored within the selected memory cell. BRIEF DESCRIPTION OF THE DRAWINGS For a detailed description of various embodiments, reference will now be made to the accompanying drawings in which: FIG. 1 shows, in block diagram form, an example computing system comprising memory structures in accordance with at least some embodiments; FIG. 2 shows, in partial block diagram form, DRAM memory cells and characteristics associated with each type of DRAM memory cell; FIG. 3 shows an example graph depicting a relationship between current and voltage in a transistor; FIG. 4a shows a DRAM memory cell and a corresponding read operation in accordance with at least some embodiments; FIG. 4b shows a DRAM memory cell and a corresponding read operation in accordance with at least some embodiments; FIG. 5a shows, in block diagram form, a time-to-transition measurement circuit in accordance with at least some embodiments; FIG. 5b shows, in block diagram form, a time-to-transition measurement circuit in accordance with at least some embodiments; FIG. 5c shows, in block diagram form, a time-to-transition measurement circuit in accordance with at least some embodiments; FIG. 6 shows a circuit configuration for a time-to-delay measurement circuit, in accordance with at least some embodiments; FIG. 7 shows a circuit configuration and timing diagrams for a time-to-delay measurement circuit in accordance with at least some embodiments; FIG. 8a shows, in block diagram form, a circuit in accordance with at least some embodiments; FIG. 8b shows, in block diagram form, a circuit in accordance with at least some embodiments; FIG. 8c shows, in block diagram form, a