US-12626756-B1 - Feedback-reinforced accelerated aging for improved PUF stability

Abstract

A method of operating a chip as an entropy source for generating a physical unclonable function (PUF) key includes: arranging in the chip a pre-amplifier array of bitcells in respective rows defined by respective pairs of true and complement wordlines and in columns defined by respective pairs of true and complement bitlines; reading, by a sense amplifier, a preferred state from a bitcell along a selected pair of the pairs of true and complement wordlines, where the pre-amplifier array of bitcells comprises the bitcell; performing feedback-reinforced accelerated aging via control circuitry in the chip including, based on the read preferred state, applying a stress condition that causes an accelerated aging effect including biasing the bitcell to the preferred state to reinforce the preferred state in the bitcell; subsequent to performing the feedback-reinforced accelerated aging, reading a value from the bitcell; and generating a PUF key using the value.

Inventors

• Eric Hunt-Schroeder
• Tian Xia

Assignees

• MARVELL ASIA PTE LTD

Dates

Publication Date

20260512

Application Date

20231214

Claims (20)

1. 1 . A method of operating a chip as an entropy source for generating a physical unclonable function (PUF) key, the method comprising: arranging in the chip a pre-amplifier array of bitcells in respective rows defined by respective pairs of true and complement wordlines and in columns defined by respective pairs of true and complement bitlines; reading, by a first sense amplifier integrated in the chip and connected to a first pair of the pairs of true and complement bitlines, a first preferred state from a first bitcell along a first selected pair of the pairs of true and complement wordlines, wherein the pre-amplifier array of bitcells comprises the first bitcell; performing feedback-reinforced accelerated aging via control circuitry in the chip including, based on the read first preferred state, applying a first stress condition that causes an accelerated aging effect in the first bitcell, wherein applying the first stress condition comprises biasing the first bitcell to the first preferred state to reinforce the first preferred state in the first bitcell; subsequent to performing the feedback-reinforced accelerated aging, reading a first value from the first bitcell; and generating a first PUF key using the first value.
2. 2 . The method according to claim 1 , wherein applying the first stress condition comprises: applying a first voltage to a first portion of the first bitcell, which is biased toward the first preferred state; and applying a second voltage to a second portion of the first bitcell, which is biased away from the first preferred state, the second voltage being less than the first voltage.
3. 3 . The method according to claim 1 , wherein applying the first stress condition comprises applying the first stress condition for longer than a threshold duration.
4. 4 . The method according to claim 1 , wherein applying the first stress condition comprises causing the first bitcell to exhibit one or more of (1) biased temperature instability or (2) hot carrier injection.
5. 5 . The method according to claim 1 , further comprising: reading, by a second sense amplifier connected to a second pair of the pairs of true and complement bitlines, a second preferred state from a second bitcell along the first selected pair of the pairs of true and complement wordlines, wherein the pre-amplifier array of bitcells comprises the second bitcell; performing feedback-reinforced accelerated aging including, based on the second preferred state, applying a second stress condition that causes an accelerated aging effect in the second bitcell, wherein applying the second stress condition comprises biasing the second bitcell to the second preferred state to reinforce the second preferred state in the second bitcell; and subsequent to performing the feedback-reinforced accelerated aging on the second bitcell, reading a second value from the first bitcell, wherein generating the first PUF key further comprises using the second value.
6. 6 . The method according to claim 5 , wherein the first stress condition and the second stress condition are applied simultaneously.
7. 7 . The method according to claim 5 , wherein: applying the first stress condition to the first bitcell comprises activating a first source voltage local to the first bitcell; and applying the second stress condition to the second bitcell comprises applying a second source voltage local to the second bitcell.
8. 8 . The method according to claim 5 , wherein applying the first stress condition to the first bitcell and applying the second stress condition to the second bitcell comprise applying a source voltage to the first selected pair of the pairs of true and complement wordlines.
9. 9 . The method according to claim 5 , further comprising, after reading the first value from the first bitcell, deactivating the first bitcell by applying a zero voltage to the true wordline of the selected pair of the pairs of true and complement wordlines and by applying a source voltage to the complement wordline of the selected pair of the pairs of true and complement wordlines to prevent the first value from being read outside of the chip.
10. 10 . A chip operating as an entropy source for generating a physical unclonable function (PUF) key, the chip comprising: a pre-amplifier array of bitcells arranged in respective rows defined by respective pairs of true and complement wordlines and in columns defined by respective pairs of true and complement bitlines; a first sense amplifier connected to a first pair of the pairs of true and complement bitlines and configured to read a first preferred state from a first bitcell of the pre-amplifier array of bitcells along a first selected pair of the pairs of true and complement wordlines; and control circuitry within the chip and configured to perform feedback-reinforced accelerated aging including, based on the read first preferred state, applying a first stress condition that causes an accelerated aging effect in the first bitcell, wherein applying the first stress condition comprises biasing the first bitcell to the first preferred state to reinforce the first preferred state in the first bitcell, wherein the first sense amplifier is further configured, subsequent to performing the feedback-reinforced accelerated aging, to read a first value from the first bitcell, and the chip further comprises key generation circuitry configured to generate a first PUF key using the first value.
11. 11 . The chip according to claim 10 , wherein the control circuitry is configured, when applying the first stress condition, to: apply a first voltage to a first portion of the first bitcell, which is biased toward the first preferred state, and apply a second voltage to a second portion of the first bitcell, which is biased away from the first preferred state, the second voltage being less than the first voltage.
12. 12 . The chip according to claim 10 , wherein the control circuitry is configured, when applying the first stress condition, to apply the first stress condition for longer than a threshold duration.
13. 13 . The chip according to claim 10 , wherein the control circuitry is configured, when applying the first stress condition, to cause the first bitcell to exhibit one or more of (1) biased temperature instability or (2) hot carrier injection.
14. 14 . The chip according to claim 10 , further comprising a second sense amplifier connected to a second pair of the pairs of true and complement bitlines and configured to read a second preferred state from a second bitcell along the first selected pair of the pairs of true and complement wordlines wherein: the pre-amplifier array of bitcells comprises the second bitcell; the control circuitry is further configured to perform feedback-reinforced accelerated aging including, based on the second preferred state, applying a second stress condition that causes an accelerated aging effect in the second bitcell, wherein applying the second stress condition comprises biasing the second bitcell to the second preferred state to reinforce the second preferred state the second bitcell; and subsequent to performing the feedback-reinforced accelerated aging on the second bitcell, the second sense amplifier is further configured to read a second value from the second bitcell; and the key generation circuitry is configured to generate the first PUF key using the second value.
15. 15 . The chip according to claim 14 , wherein the control circuitry is further configured to apply the first stress condition and the second stress condition simultaneously.
16. 16 . The chip according to claim 14 , wherein the control circuitry is further configured to: when applying the first stress condition to the first bitcell, activate a first source voltage local to the first bitcell; and when applying the second stress condition to the second bitcell, apply a second source voltage local to the second bitcell.
17. 17 . The chip according to claim 14 , wherein the control circuitry is further configured to, when applying the first stress condition to the first bitcell and applying the second stress condition to the second bitcell, apply a source voltage to the first selected pair of true and complement wordlines.
18. 18 . The chip according to claim 10 , wherein the control circuitry is further configured to, after reading the first value from the first bitcell, deactivate the first bitcell by applying a zero voltage to the true wordline of the selected pair of true and complement wordlines and by applying a source voltage to the complement wordline of the selected pair of true and complement wordlines to prevent the first value from being read outside of the chip.
19. 19 . The chip of claim 10 , wherein the first sense amplifier is configured, in reading the first preferred state, to: sense a state of the first bitcell; and output the first preferred state based on the sensed state of the first bitcell.
20. 20 . The chip of claim 10 , further comprising imbalance circuitry connected to the pairs of true and complement bitlines, wherein the control circuitry is connected to the first sense amplifier and provides feedback to the imbalance circuitry.

Description

CROSS REFERENCE TO RELATED APPLICATIONS This disclosure claims the benefit of commonly-assigned U.S. Provisional Patent Application No. 63/432,859, filed Dec. 15, 2022, which is hereby incorporated by reference herein in its entirety. FIELD OF USE This disclosure relates to stabilizing bitcells for generating a PUF key. More particularly, this disclosure relates to applying accelerated aging to a bitcell. BACKGROUND The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the inventors hereof, to the extent that that work is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted to be prior art against the subject matter of the present disclosure. Physical Unclonable Functions (PUFs) generate secure encryption keys for a semiconductor device based on intrinsic process variations in the fabrication of the device. PUFs are used for chip authentication through a random, unique, and repeatable on-chip secret key that is generated on request. The ability to reliably regenerate the PUF key under any test condition is extremely difficult. Many designs suggest PUF key error rates (KER), which measure the probability of a bit flipping values, at 10−6. SUMMARY In accordance with implementations of the subject matter of this disclosure, a method for reinforcing an unstable bitcell in an entropy source, for use in generating a physical unclonable function (PUF) key, includes arranging an array of bitcells in respective rows defined by respective pairs of true and complement wordlines and in columns defined by respective pairs of true and complement bitlines, reading, by a first sense amplifier connected to a first pair of true and complement bitlines, a first preferred state from a first bitcell along a first selected pair of true and complement wordlines, determining a first stress condition that causes an accelerated aging effect in the first bitcell which biases the first bitcell to the first preferred state for the first bitcell, applying the first stress condition to the first bitcell, reading a first value from the first bitcell, and generating a first PUF key using the first value. In a first implementation of such a method, applying the first stress condition may include applying a first voltage to a first portion of the first bitcell which is biased toward the first preferred state for the first bitcell, and applying a second voltage lower than the first voltage to a second portion of the first bitcell which is biased away from the first preferred state for the first bitcell. In a second implementation of such a method, applying the first stress condition may include applying the first stress condition for longer than a threshold duration. In a second implementation of such a method, applying the first stress condition may include causing the unstable bitcell to exhibit one or more of (1) biased temperature instability or (2) hot carrier injection. A third implementation of such a method may further include reading, by a second sense amplifier connected to a second pair of true and complement bitlines, a second preferred state from a second bitcell along the first selected pair of true and complement wordlines, determining a second stress condition that causes an accelerated aging effect in the second bitcell which biases the second bitcell to the second preferred state for the second bitcell, and applying the second stress condition to the second bitcell, and reading a second value from the first bitcell, where generating the first PUF key may further include using the second value. According to a first aspect of that third implementation, the first stress condition and the second stress condition may be applied simultaneously. According to a second aspect of that third implementation, applying the first stress condition to the first bitcell may include activating a first source voltage local to the first bitcell and applying the second stress condition to the second bitcell may include applying a second source voltage local to the second bitcell. According to a third aspect of that third implementation, applying the first stress condition to the first bitcell and applying the second stress condition to the second bitcell may include applying a voltage source to the first selected pair of true and complement wordlines. A fourth aspect of that third implementation may further include, after reading the first value from the first bitcell, deactivating the first bitcell by applying a zero voltage to the true wordline of the selected pair of true and complement wordlines and a source voltage to the complement wordline of the selected pair of true and complement wordlines to prevent the first value from being read outside of the entropy source. In accordance with implementations of the subject matter of this disclosu