US-12626759-B1 - Error correction for identifier data generated from unclonable characteristics of resistive memory

US12626759B1US 12626759 B1US12626759 B1US 12626759B1US-12626759-B1

Abstract

Leveraging stochastic physical characteristics of resistive switching devices to generate data having very low cross correlation among bits of that data is disclosed. Data generated from stochastic physical characteristics can also be referred to as physical unclonable feature—or function—(PUF) data. Additionally, error correction functions for PUF data generated from resistive switching memory cells are provided. The error correction functions facilitate additional redundancy and longevity of PUF data, among other benefits. Different embodiments include addressing arrangements to incorporate ECC parity bits among generated PUF data bits, even for differential PUF bits respectively defined by multiple memory cells in different portions of a resistive memory array.

Inventors

Mehdi Asnaashari

Assignees

Crossbar, Inc.

Dates

Publication Date: 20260512
Application Date: 20240112

Claims (5)

1 . An integrated circuit device, comprising: a resistive switching memory array comprising a plurality of resistive switching devices disposed overlying a substrate; a control circuit for segregating a subset of the plurality of resistive switching devices thereby defining a first subset of the resistive switching devices; an error correction control (ECC) encoder configured to generate correction data for data at the resistive switching memory array; and a sensing circuit disposed at least in part on the substrate and electrically coupled to the plurality of resistive switching devices, wherein the sensing circuit is configured to selectively apply a sense signal to a first resistive switching device of the first subset of the resistive switching devices, wherein the sensing circuit is configured to determine a first response signal from the first resistive switching device in response to the sense signal, and wherein the sensing circuit is configured to selectively apply the sense signal to a second resistive switching device of the first subset of the resistive switching devices, wherein the sensing circuit is configured to determine a second response signal from the second resistive switching device in response to the sense signal, wherein: the control circuit defines a bit for the combination of the first resistive switching device and the second resistive switching device, the control circuit establishes a logic value for the bit based on the first response signal and second response signal, the control circuit establishes additional logic values for additional bits defined for respective additional pairs of the first subset of the resistive switching devices, the respective additional pairs excluding the first resistive switching device or excluding the second resistive switching device, and the bit and the additional bits defining a sequence of data, and the ECC encoder generates error correction data corresponding to the sequence of data.
2 . The integrated circuit device of claim 1 , wherein each of the plurality of resistive switching devices is associated with an operational programming characteristic having low correlation among resistive switching devices of the plurality of resistive switching devices and wherein the low correlation is defined by a correlation coefficient within a range of about −0.1 to about 0.1.
3 . The integrated circuit device of claim 1 , further comprising a command and data interface for receiving a command from a host device specifying an address associated with the plurality of resistive switching devices, and specifying a command causing the control circuit to select the first subset of the resistive switching devices from the address.
4 . The integrated circuit device of claim 1 , wherein the sensing circuit is configured to read the sequence of data and provide the sequence of data to the ECC encoder to generate the error correction data.
5 . The integrated circuit device of claim 1 , wherein the control circuit is configured to at least one of: apply a strong program pulse to the first resistive switching device in response to the first response signal being a program response; or apply the strong program pulse to the second resistive switching device in response to the second response signal being the program response.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application for patent is a divisional of and claims priority to U.S. application Ser. No. 17/708,541, titled ERROR CORRECTION FOR IDENTIFIER DATA GENERATED FROM UNCLONABLE CHARACTERISTICS OF RESISTIVE MEMORY and filed Mar. 30, 2022, which is hereby incorporated by reference herein in its entirety and for all purposes. INCORPORATION BY REFERENCE Each of the following: U.S. patent application Ser. No. 17/223,817 filed Apr. 6, 2021, U.S. patent application Ser. No. 17/223,816 filed Apr. 6, 2021, U.S. patent application Ser. No. 17/223,824 filed Apr. 6, 2021 and U.S. Provisional Patent Application No. 63/005,879 filed Apr. 6, 2020 are hereby incorporated by reference herein in their respective entireties and for all purposes. TECHNICAL FIELD The subject disclosure relates generally to two-terminal resistive switching memory, and as one illustrative example, providing error correction for identifier data formed from stochastic characteristics of resistive switching memory cells. BACKGROUND Resistive-switching memory represents a recent innovation within the field of integrated circuit technology. While much of resistive-switching memory technology is in the development stage, various technological concepts for resistive-switching memory have been demonstrated and are in one or more stages of verification to prove or disprove associated theories or techniques. Resistive-switching memory technology is expected to show compelling evidence of substantial advantages over competing technologies in the semiconductor electronics industry in the near future. Proposals for practical utilization of resistive-switching technology to memory applications for electronic devices have been put forth. For instance, resistive-switching elements are often theorized as viable alternatives, at least in part, to metal-oxide semiconductor (MOS) type memory transistors employed for electronic storage of digital information. Models of resistive-switching memory devices provide some potential technical advantages over non-volatile FLASH MOS type transistors, for instance. Monolithic integration of resistive-switching memory within integrated circuit processes has been supported by other proposed models. Some models of resistive-switching memory are designed for front-end-of-line processing on a substrate, whereas other models are designed for back-end-of-line processing above the substrate. As a result, resistive-switching memory is expected to be compatible with embedded memory applications to support various integrated circuit devices as well as a stand-alone integrated circuit memory chip. In light of the above, the Assignee of the present disclosure continues to develop and pursue practical utilizations of resistive-switching technology. SUMMARY The following presents a simplified summary of the specification in order to provide a basic understanding of some aspects of the specification. This summary is not an extensive overview of the specification. It is intended to neither identify key or critical elements of the specification nor delineate the scope of any particular embodiments of the specification, or any scope of the claims. Its purpose is to present some concepts of the specification in a simplified form as a prelude to the more detailed description that is presented in this disclosure. Embodiments of the present disclosure provide for leveraging physical characteristics of resistive switching devices to generate data having very low cross correlation among bits of that data. Such data can be utilized for identifier data for identifying a chip (chip ID), a cryptographic key for security functions such as Elliptic curve cryptography, Advanced Encryption System (AES), and HMAC, and the like. Further embodiments disclose providing error correction functions for data generated from physical characteristics of the resistive switching device. Error correction functions can include error correction code for controlling data errors pertaining to such data. Examples of suitable error correction code can include Hamming code or other block code (e.g., Reed-Solomon code, Golay code, BCH, multidimensional parity code, low density parity check (LDPC) code, and so forth), convolutional code (e.g., Viterbi algorithm, MAP algorithm, BCJR algorithm, etc.), forward error correction code (e.g., Marker code, Watermark code, and so forth), among many other error correction codes. In an embodiment, disclosed is a method of operating a resistive memory array of an integrated circuit device. The method can comprise identifying a set of resistive memory bits of the resistive memory array to form a data sequence from native physical characteristics of the resistive memory bits, initiate a formation pulse on the set of resistive memory bits and terminate the formation pulse in response to detecting a termination condition selected to program a portion of the set of resistive memory bits. Moreover, the method