US-12626760-B2 - Memory circuitry and method used in forming memory circuitry that has an insulator tier directly below a lowest upper first tier and directly above an uppermost lower first tier

US12626760B2US 12626760 B2US12626760 B2US 12626760B2US-12626760-B2

Abstract

A method used in forming a memory array comprising strings of memory cells comprises forming a lower stack comprising vertically-alternating different-composition lower first tiers and lower second tiers. The lower stack comprises lower channel-material strings extending through the lower first tiers and the lower second tiers. An upper stack is formed directly above the lower stack. The upper stack comprises vertically-alternating different-composition upper first tiers and upper second tiers. The upper stack comprises upper channel-material strings of select-gate transistors. Individual of the upper channel-material strings are directly electrically coupled to individual of the lower channel-material strings. The upper and lower first tiers are conductive at least in a finished-circuitry construction. The upper and lower second tiers are insulative and comprise insulative material. An insulator tier comprising insulator material is directly below a lowest of the upper first tiers and directly above an uppermost of the lower first tiers. The insulator material is of different composition from that of the insulative material of the upper second tiers and of different composition from that of the insulative material of the lower second tiers. Other embodiments, including structure, are disclosed.

Inventors

Jiewei CHEN
Shuangqiang Luo
Lifang Xu

Assignees

MICRON TECHNOLOGY, INC.

Dates

Publication Date: 20260512
Application Date: 20220805

Claims (20)

1 . A method used in forming a memory array comprising strings of memory cells, comprising: forming a lower stack comprising vertically-alternating different-composition lower first tiers and lower second tiers, the lower stack comprising lower channel-material strings extending through the lower first tiers and the lower second tiers; forming an upper stack directly above the lower stack, the upper stack comprising vertically-alternating different-composition upper first tiers and upper second tiers, the upper stack comprising upper channel-material strings of select-gate transistors, individual of the upper channel-material strings being directly electrically coupled to individual of the lower channel-material strings, the upper and lower first tiers being conductive at least in a finished-circuitry construction, the upper and lower second tiers being insulative and comprising insulative material; and an insulator tier comprising insulator material directly below a lowest of the upper first tiers and directly above an uppermost of the lower first tiers, the insulator material being of different composition from that of the insulative material of the upper second tiers and of different composition from that of the insulative material of the lower second tiers, the insulator tier comprising insulating material of different composition from that of the insulator material and that is both directly above and directly below the insulator material, the insulating material that is directly below the insulator material being laterally alongside both of the upper and lower channel-material strings.
2 . The method of claim 1 comprising etching horizontally-elongated trenches through the upper first and second tiers to form sub-blocks and using the insulator material of the insulator tier as an etch-stop to form a bottom of individual of the horizontally-elongated trenches to be atop or within the insulator material of the insulator tier.
3 . The method of claim 1 wherein the insulative material of the upper second tiers and the insulative material of the lower second tiers are of the same composition relative one another.
4 . The method of claim 1 wherein the insulator material comprises at least one of carbon-doped silicon nitride, carbon-doped hafnium oxide, boron, carbon-doped boron, boron oxide, carbon-doped boron oxide, zirconium oxide, carbon-doped zirconium oxide, aluminum oxide, and carbon-doped aluminum oxide.
5 . A method used in forming a memory array comprising strings of memory cells, comprising: forming a lower stack comprising vertically-alternating different-composition lower first tiers and lower second tiers, the lower stack comprising lower channel-material strings extending through the lower first tiers and the lower second tiers; forming an upper stack directly above the lower stack, the upper stack comprising vertically-alternating different-composition upper first tiers and upper second tiers, the upper stack comprising upper channel-material strings of select-gate transistors, individual of the upper channel-material strings being directly electrically coupled to individual of the lower channel-material strings, the upper and lower first tiers being conductive at least in a finished-circuitry construction, the upper and lower second tiers being insulative and comprising insulative material; an insulator tier comprising insulator material directly below a lowest of the upper first tiers and directly above an uppermost of the lower first tiers, the insulator material being of different composition from that of the insulative material of the upper second tiers and of different composition from that of the insulative material of the lower second tiers; the upper and lower first tiers comprise conducting material in the finished-circuitry construction; the insulator material is directly against the conducting material of the lowest upper first tier; and the insulator material is directly against the conducting material of the uppermost lower first tier.
6 . The method of claim 5 wherein the insulator material is homogenous.
7 . A method used in forming a memory array comprising strings of memory cells, comprising: forming a lower stack comprising vertically-alternating different-composition lower first tiers and lower second tiers, the lower stack comprising lower channel-material strings extending through the lower first tiers and the lower second tiers; forming an upper stack directly above the lower stack, the upper stack comprising vertically-alternating different-composition upper first tiers and upper second tiers, the upper stack comprising upper channel-material strings of select-gate transistors, individual of the upper channel-material strings being directly electrically coupled to individual of the lower channel-material strings, the upper and lower first tiers being conductive at least in a finished-circuitry construction, the upper and lower second tiers being insulative; and an insulator tier comprising insulator material directly below a lowest of the upper first tiers and directly above an uppermost of the lower first tiers; the insulator material comprising at least one of carbon-doped silicon nitride, carbon-doped hafnium oxide, boron, carbon-doped boron, boron oxide, carbon-doped boron oxide, carbon-doped zirconium oxide, and carbon-doped aluminum oxide.
8 . The method of claim 7 comprising only one of the at least one.
9 . The method of claim 7 comprising more than one of the at least one.
10 . The method of claim 7 comprising etching horizontally-elongated trenches through the upper first and second tiers to form sub-blocks and using the insulator material of the insulator tier as an etch-stop to form a bottom of individual of the horizontally-elongated trenches to be atop or within the insulator material of the insulator tier.
11 . The method of claim 7 wherein the insulator tier comprises insulating material of different composition from that of the insulator material and that is at least one of directly above and directly below the insulator material.
12 . A method used in forming a memory array comprising strings of memory cells, comprising: forming a lower stack comprising vertically-alternating different-composition lower first tiers and lower second tiers, the lower stack comprising lower channel-material strings extending through the lower first tiers and the lower second tiers; forming an upper stack directly above the lower stack, the upper stack comprising vertically-alternating different-composition upper first tiers and upper second tiers, the upper stack comprising upper channel-material strings of select-gate transistors, individual of the upper channel-material strings being directly electrically coupled to individual of the lower channel-material strings, the upper and lower first tiers being conductive at least in a finished-circuitry construction, the upper and lower second tiers being insulative; and an insulator tier comprising insulator material directly below a lowest of the upper first tiers and directly above an uppermost of the lower first tiers; the insulator material comprising at least one of carbon-doped silicon nitride, carbon-doped hafnium oxide, boron, carbon-doped boron, boron oxide, carbon-doped boron oxide, zirconium oxide, carbon-doped zirconium oxide, aluminum oxide, and carbon-doped aluminum oxide; the upper and lower first tiers comprise conducting material in the finished-circuitry construction; the insulator material is directly against the conducting material of the lowest upper first tier; and the insulator material is directly against the conducting material of the uppermost lower first tier.
13 . The memory array of claim 12 wherein the insulator material comprises carbon-doped aluminum oxide.
14 . The memory array of claim 12 wherein the insulator material comprises carbon-doped silicon nitride.
15 . The memory array of claim 12 wherein the insulator material comprises carbon-doped hafnium oxide.
16 . The memory array of claim 12 wherein the insulator material comprises boron.
17 . The memory array of claim 12 wherein the insulator material comprises carbon-doped boron.
18 . The memory array of claim 12 wherein the insulator material comprises boron oxide.
19 . The memory array of claim 12 wherein the insulator material comprises carbon-doped boron oxide.
20 . The memory array of claim 12 wherein the insulator material comprises carbon-doped zirconium oxide.

Description

TECHNICAL FIELD Embodiments disclosed herein pertain to memory circuitry and to methods used in forming memory circuitry. BACKGROUND Memory is one type of integrated circuitry and is used in computer systems for storing data. Memory may be fabricated in one or more arrays of individual memory cells. Memory cells may be written to, or read from, using digitlines (which may also be referred to as bitlines, data lines, or sense lines) and access lines (which may also be referred to as wordlines). The sense lines may conductively interconnect memory cells along columns of the array, and the access lines may conductively interconnect memory cells along rows of the array. Each memory cell may be uniquely addressed through the combination of a sense line and an access line. Memory cells may be volatile, semi-volatile, or non-volatile. Non-volatile memory cells can store data for extended periods of time in the absence of power. Non-volatile memory is conventionally specified to be memory having a retention time of at least about 10 years. Volatile memory dissipates and is therefore refreshed/rewritten to maintain data storage. Volatile memory may have a retention time of milliseconds or less. Regardless, memory cells are configured to retain or store memory in at least two different selectable states. In a binary system, the states are considered as either a “0” or a “1”. In other systems, at least some individual memory cells may be configured to store more than two levels or states of information. A field effect transistor is one type of electronic component that may be used in a memory cell. These transistors comprise a pair of conductive source/drain regions having a semiconductive channel region there-between. A conductive gate is adjacent the channel region and separated there-from by a thin gate insulator. Application of a suitable voltage to the gate allows current to flow from one of the source/drain regions to the other through the channel region. When the voltage is removed from the gate, current is largely prevented from flowing through the channel region. Field effect transistors may also include additional structure, for example a reversibly programmable charge-storage region as part of the gate construction between the gate insulator and the conductive gate. Flash memory is one type of memory and has numerous uses in modern computers and devices. For instance, modern personal computers may have BIOS stored on a flash memory chip. As another example, it is becoming increasingly common for computers and other devices to utilize flash memory in solid state drives to replace conventional hard drives. As yet another example, flash memory is popular in wireless electronic devices because it enables manufacturers to support new communication protocols as they become standardized, and to provide the ability to remotely upgrade the devices for enhanced features. NAND may be a basic architecture of integrated flash memory. A NAND cell unit comprises at least one selecting device coupled in series to a serial combination of memory cells (with the serial combination commonly being referred to as a NAND string). NAND architecture may be configured in a three-dimensional arrangement comprising vertically-stacked memory cells individually comprising a reversibly programmable vertical transistor. Control or other circuitry may be formed below the vertically-stacked memory cells. Other volatile or non-volatile memory array architectures may also comprise vertically-stacked memory cells that individually comprise a transistor. Memory arrays may be arranged in memory pages, memory blocks and partial blocks (e.g., sub-blocks), and memory planes, for example as shown and described in any of U.S. Patent Application Publication Nos. 2015/0228651, 2016/0267984, and 2017/0140833. The memory blocks may at least in part define longitudinal outlines of individual wordlines in individual wordline tiers of vertically-stacked memory cells. Connections to these wordlines may occur in a so-called “stair-step structure” at an end or edge of an array of the vertically-stacked memory cells. The stair-step structure includes individual “stairs” (alternately termed “steps” or “stair-steps”) that define contact regions of the individual wordlines upon which elevationally-extending conductive vias contact to provide electrical access to the wordlines. BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1-4 are diagrammatic cross-sectional views of portions of a construction that will comprise an array of elevationally-extending strings of memory cells in accordance with an embodiment of the invention. FIGS. 5-17 are diagrammatic sequential sectional and/or enlarged views of the construction of FIGS. 1-4, or portions thereof or alternate and/or additional embodiments, in process in accordance with some embodiments of the invention. DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS Embodiments of the invention encompass methods used in forming a memory array