US-12626761-B2 - Memory circuitry and method used in forming memory circuitry

US12626761B2US 12626761 B2US12626761 B2US 12626761B2US-12626761-B2

Abstract

Memory circuitry comprising strings of memory cells comprises a stack comprising vertically-alternating insulative tiers and conductive tiers. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers in a memory-array region. The insulative tiers and the conductive tiers extend from the memory-array region into a stair-step region. The stair-step region comprises a cavity comprising a flight of stairs extending along a first direction. Multiple different-depth and height-sequential treads in individual of the stairs extend along a second direction that is orthogonal to the first direction. Individual of the multiple different-depth treads comprise conducting material of one of the conductive tiers. The cavity comprises a pair of laterally-opposing outermost sidewalls relative to the second direction and that individually extend along the first direction. The multiple different-depth and height-sequential treads in the individual stairs comprise a single flight of said treads that extends along the second direction from one of the laterally-opposing outermost sidewalls to the other of the laterally-opposing outermost sidewalls. Methods are disclosed.

Inventors

John D. Hopkins
Alyssa N. Scarbrough

Assignees

MICRON TECHNOLOGY, INC.

Dates

Publication Date: 20260512
Application Date: 20220829

Claims (20)

1 . A method used in forming memory circuitry, comprising: forming a stack comprising vertically-alternating first tiers and second tiers, the stack extending from a memory-array region into a stair-step region, the stair-step region comprising a cavity comprising a flight of stairs extending along a first direction, the first tiers being conductive and the second tiers being insulative at least in a finished-circuitry construction, the cavity comprising a pair of laterally-opposing outermost sidewalls relative to a second direction that is orthogonal to the first direction and that individually extend along the first direction; forming a series of first and second spacers in the cavity, the first and second spacers extending along the first direction directly above the flight of stairs, the first spacers having a different composition than the second spacers, the series of spacers having first spacers alternating with second spacers along the second direction; forming masking material directly above the series of first and second spacers, the masking material comprising an opening there-through that exposes a single spacer of the first and second spacers, the single spacer being laterally-closest to one of the laterally-opposing outermost sidewalls, the masking material covering all remaining of the first and second spacers; and using the masking material in a plurality of alternating etching and lateral-trimming steps that progressively widen the opening and form multiple different-depth treads in individual of the stairs along the second direction, each of the lateral-trimming steps individually exposing a single next-in-series spacer comprised by the series of first and second spacers through the masking material and covering all then-remaining, if any, of the first and second spacers with the masking material, the etching steps individually removing only one of the alternating first and second spacers as a result of the respective lateral-trimming step followed by etching through one of the first tiers and one of the second tiers that was there-below, individual of the treads comprising conducting material of individual of the first tiers in the finished-circuitry construction.
2 . The method of claim 1 wherein forming at least some of the series of first and second spacers comprises: forming a spacer-forming layer above and within the cavity; and anisotropically etching the spacer-forming layer above and within the cavity.
3 . The method of claim 2 wherein less-than-all of the spacers are formed by anisotropically etching the respective spacer-forming layer within the cavity.
4 . The method of claim 3 wherein a majority of the collective first and second spacers is formed by the anisotropically etching of the respective spacer-forming layer within the cavity.
5 . The method of claim 1 wherein the masking material comprises photoresist.
6 . The method of claim 1 wherein each of the different compositions is different from those of the first and second tiers.
7 . The method of claim 1 wherein one of the different compositions is carbon.
8 . The method of claim 1 wherein one of the different compositions is polysilicon.
9 . The method of claim 1 wherein one of the different compositions is carbon and the other of the different compositions is polysilicon.
10 . The method of claim 1 wherein total number of the alternating first and second spacers in the cavity is five.
11 . The method of claim 1 wherein the individual stairs have total number of the multiple different-depth treads in the finished-circuitry construction that is five.
12 . The method of claim 1 wherein, total number of the alternating first and second spacers in the series is five; and the individual stairs have total number of the multiple different-depth treads in the finished-circuitry construction that is five.
13 . The method of claim 1 wherein the multiple different-depth treads in the finished-circuitry construction are height-sequential along the second direction in the individual stairs.
14 . The method of claim 13 wherein the multiple different-depth and height-sequential treads in the individual stairs comprise a single flight of said treads that extends along the second direction from one of the laterally-opposing outermost sidewalls to the other of the laterally-opposing outermost sidewalls.
15 . The method of claim 14 wherein the individual stairs have total number of the multiple different-depth treads in the finished-circuitry construction that is five.
16 . The method of claim 1 wherein the first and second spacers are of the same lateral-width in the second direction.
17 . A method used in forming memory circuitry, comprising: forming a stack comprising vertically-alternating first tiers and second tiers, the stack extending from a memory-array region into a stair-step region, the stair-step region comprising a cavity comprising a flight of stairs extending along a first direction, the first tiers being conductive and the second tiers being insulative at least in a finished-circuitry construction, the cavity comprising a pair of laterally-opposing outermost sidewalls relative to a second direction that is orthogonal to the first direction and that individually extend along the first direction; forming fill material in the cavity directly above the flight of stairs; forming masking material directly above the fill material, the masking material comprising an opening there-through that exposes a portion of the fill material that is laterally-closest to one of the laterally-opposing outermost sidewalls and extends there-along in the first direction, the masking material covering all remaining of the fill material but for the portion; and using the masking material in a plurality of alternating etching and lateral-trimming steps that progressively widen the opening from the laterally-closest sidewall along the first direction and form multiple different-depth treads in individual of the stairs along the second direction, the lateral-trimming steps individually exposing a next-in-succession portion of the fill material that extends along the first direction and covering all then-remaining, if any, of the fill material, the etching steps individually removing the respective next-in-succession portion as a result of the respective lateral-trimming step followed by etching through one of the first tiers and one of the second tiers that was there-below, individual of the treads comprising conducting material of individual of the first tiers in the finished-circuitry construction.
18 . The method of claim 17 wherein the masking material comprises photoresist.
19 . The method of claim 17 wherein the individual stairs have total number of the multiple different-depth treads that is five.
20 . The method of claim 17 wherein the multiple different-depth treads in in the finished-circuitry construction are height-sequential along the second direction in the individual stairs.

Description

TECHNICAL FIELD Embodiments disclosed herein pertain to memory circuitry and to methods used in forming memory circuitry. BACKGROUND Memory is one type of integrated circuitry and is used in computer systems for storing data. Memory may be fabricated in one or more arrays of individual memory cells. Memory cells may be written to, or read from, using digitlines (which may also be referred to as bitlines, data lines, or sense lines) and access lines (which may also be referred to as wordlines). The sense lines may conductively interconnect memory cells along columns of the array, and the access lines may conductively interconnect memory cells along rows of the array. Each memory cell may be uniquely addressed through the combination of a sense line and an access line. Memory cells may be volatile, semi-volatile, or non-volatile. Non-volatile memory cells can store data for extended periods of time in the absence of power. Non-volatile memory is conventionally specified to be memory having a retention time of at least about 10 years. Volatile memory dissipates and is therefore refreshed/rewritten to maintain data storage. Volatile memory may have a retention time of milliseconds or less. Regardless, memory cells are configured to retain or store memory in at least two different selectable states. In a binary system, the states are considered as either a “0” or a “1”. In other systems, at least some individual memory cells may be configured to store more than two levels or states of information. A field effect transistor is one type of electronic component that may be used in a memory cell. These transistors comprise a pair of conductive source/drain regions having a semiconductive channel region there-between. A conductive gate is adjacent the channel region and separated there-from by a thin gate insulator. Application of a suitable voltage to the gate allows current to flow from one of the source/drain regions to the other through the channel region. When the voltage is removed from the gate, current is largely prevented from flowing through the channel region. Field effect transistors may also include additional structure, for example a reversibly programmable charge-storage region as part of the gate construction between the gate insulator and the conductive gate. Flash memory is one type of memory and has numerous uses in modern computers and devices. For instance, modern personal computers may have BIOS stored on a flash memory chip. As another example, it is becoming increasingly common for computers and other devices to utilize flash memory in solid state drives to replace conventional hard drives. As yet another example, flash memory is popular in wireless electronic devices because it enables manufacturers to support new communication protocols as they become standardized, and to provide the ability to remotely upgrade the devices for enhanced features. NAND may be a basic architecture of integrated flash memory. A NAND cell unit comprises at least one selecting device coupled in series to a serial combination of memory cells (with the serial combination commonly being referred to as a NAND string). NAND architecture may be configured in a three-dimensional arrangement comprising vertically-stacked memory cells individually comprising a reversibly programmable vertical transistor. Control or other circuitry may be formed below the vertically-stacked memory cells. Other volatile or non-volatile memory array architectures may also comprise vertically-stacked memory cells that individually comprise a transistor. Memory arrays may be arranged in memory pages, memory blocks and partial blocks (e.g., sub-blocks), and memory planes, for example as shown and described in any of U.S. Patent Application Publication Nos. 2015/0228651, 2016/0267984, and 2017/0140833. The memory blocks may at least in part define longitudinal outlines of individual wordlines in individual wordline tiers of vertically-stacked memory cells. Connections to these wordlines may occur in a so-called “stair-step structure” at an end or edge of an array of the vertically-stacked memory cells. The stair-step structure includes individual “stairs” (alternately termed “steps” or “stair-steps”) that define contact regions of the individual wordlines upon which elevationally-extending conductive vias contact to provide electrical access to the wordlines. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagrammatic view of a portion of memory circuitry in process in accordance with embodiments of the invention. FIG. 3 is a diagrammatic cross-sectional view taken through line 3-3 in FIG. 1. FIGS. 2 and 4-39 are diagrammatic sectional, expanded, enlarged, and/or partial views of the construction of FIGS. 1-3 or portions thereof, and/or of alternate embodiments. DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS Embodiments of the invention encompass methods used in forming integrated circuitry, for example memory circuitry comprising a memory array, for