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US-12626762-B2 - Memory device structure and fabrication method

US12626762B2US 12626762 B2US12626762 B2US 12626762B2US-12626762-B2

Abstract

A three-dimensional (3D) memory device includes an array wafer having a memory array layer and a complementary metal-oxide-semiconductor (CMOS) layer stacked together, the CMOS layer having high-voltage (HV) circuitry of a plurality of peripheral devices, and the memory array layer having a plurality of memory cells and a stair structure. The memory array layer includes at least one cell region for forming the memory cells and at least one stair structure region for forming the stair structure, and the CMOS layer includes at least one driver region. The 3D memory device further includes CMOS wafer having low-voltage (LV) circuitry and low-low-voltage (LLV) circuitry of the plurality of peripheral devices. The CMOS wafer includes at least one page buffer region. The array wafer and the CMOS wafer are bonded at a bonding interface.

Inventors

  • Liang Chen
  • Wei Liu

Assignees

  • YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Dates

Publication Date
20260512
Application Date
20221228

Claims (16)

  1. 1 . A three-dimensional (3D) memory device, comprising: an array wafer having a memory array layer and a complementary metal-oxide-semiconductor (CMOS) layer stacked together, the CMOS layer having high-voltage (HV) circuitry of a plurality of peripheral devices, and the memory array layer having a plurality of memory cells and a stair structure, wherein the memory array layer includes at least one cell region for forming the memory cells and at least one stair structure region for forming the stair structure, and the CMOS layer includes at least one driver region; and a CMOS wafer having low-voltage (LV) circuitry and low-low-voltage (LLV) circuitry of the plurality of peripheral devices, wherein the CMOS wafer includes at least one page buffer region, wherein the array wafer and the CMOS wafer are bonded at a bonding interface; the bonding interface is between a CMOS joint layer of the CMOS wafer and an array joint layer of the array wafer; and the CMOS joint layer of the CMOS wafer and the array joint layer of the array wafer are bonded, and one or more joint structures on the array joint layer of the array wafer and one or more joint structures on the CMOS joint layer of the CMOS wafer are bonded together for electrical connection, and a vertical projection of the at least one page buffer region of the CMOS wafer fits within a vertical projection of the at least one cell region of the memory array layer.
  2. 2 . The 3D memory device according to claim 1 , wherein: the CMOS wafer includes a plurality of page buffers formed in the at least one page buffer region, including HV circuits of the page buffers, and the at least one page buffer region corresponds to the at least one cell region; and the CMOS layer includes a driver formed in the at least one driver region, and the driver region corresponds to the at least one stair structure region.
  3. 3 . A three-dimensional (3D) memory device, comprising: an array wafer having a memory array layer and a complementary metal-oxide-semiconductor (CMOS) layer stacked together, the CMOS layer having high-voltage (HV) circuitry of a plurality of peripheral devices, and the memory array layer having a plurality of memory cells and a stair structure, wherein the memory array layer includes at least one cell region for forming the memory cells and at least one stair structure region for forming the stair structure, and the CMOS layer includes at least one driver region; and a CMOS wafer having low-voltage (LV) circuitry and low-low-voltage (LLV) circuitry of the plurality of peripheral devices, wherein the CMOS wafer includes at least one page buffer region, wherein the array wafer and the CMOS wafer are bonded at a bonding interface; the CMOS wafer includes a plurality of page buffers formed in the at least one page buffer region, including HV circuits of the page buffers, and the at least one page buffer region corresponds to the at least one cell region; the CMOS layer includes a driver formed in the at least one driver region, and the driver region corresponds to the at least one stair structure region; the at least one cell region is a single center portion of the memory array layer, and the at least one stair structure region are two side portions of the memory array layer; the at least one page buffer region is a single center portion of the CMOS wafer; and the at least one driver region are two side portions of the CMOS layer.
  4. 4 . A three-dimensional (3D) memory device, comprising: an array wafer having a memory array layer and a complementary metal-oxide-semiconductor (CMOS) layer stacked together, the CMOS layer having high-voltage (HV) circuitry of a plurality of peripheral devices, and the memory array layer having a plurality of memory cells and a stair structure, wherein the memory array layer includes at least one cell region for forming the memory cells and at least one stair structure region for forming the stair structure, and the CMOS layer includes at least one driver region; and a CMOS wafer having low-voltage (LV) circuitry and low-low-voltage (LLV) circuitry of the plurality of peripheral devices, wherein the CMOS wafer includes at least one page buffer region, wherein the array wafer and the CMOS wafer are bonded at a bonding interface; the CMOS wafer includes a plurality of page buffers formed in the at least one page buffer region, including HV circuits of the page buffers, and the at least one page buffer region corresponds to the at least one cell region; the CMOS layer includes a driver formed in the at least one driver region, and the driver region corresponds to the at least one stair structure region; the at least one cell region are two side portions of the memory array layer, and the at least one stair structure region is a single center portion of the memory array layer; the at least one page buffer region are two side portions of the CMOS wafer; and the at least one driver region is a single center portion of the CMOS layer.
  5. 5 . The 3D memory device according to claim 2 , wherein the CMOS layer is formed based on a peripheral-under-chip (PUC) mechanism, and the CMOS layer is located under the memory array layer and separated by a base layer for forming the memory array layer.
  6. 6 . The 3D memory device according to claim 5 , wherein the base layer is a polysilicon layer, the array wafer includes a first substrate, the CMOS layer comprises a device layer formed on the first substrate, the polysilicon layer is formed on the device layer of the CMOS layer, and the memory array layer is formed on the polysilicon layer.
  7. 7 . The 3D memory device according to claim 6 , wherein the CMOS wafer includes a second substrate for forming HV circuits of the page buffers and the low-voltage (LV) circuitry and low-low-voltage (LLV) circuitry of the plurality of peripheral devices.
  8. 8 . The 3D memory device according to claim 1 , wherein the 3D memory device further comprises: an insulating layer formed over the second substrate; at least one through substrate contact penetrating the second substrate; and at least one array pad in contact with the at least one through substrate contact.
  9. 9 . The 3D memory device according to claim 3 , wherein the CMOS layer is formed based on a peripheral-under-chip (PUC) mechanism, and the CMOS layer is located under the memory array layer and separated by a base layer for forming the memory array layer.
  10. 10 . The 3D memory device according to claim 9 , wherein the base layer is a polysilicon layer, the array wafer includes a first substrate, the CMOS layer comprises a device layer formed on the first substrate, the polysilicon layer is formed on the device layer of the CMOS layer, and the memory array layer is formed on the polysilicon layer.
  11. 11 . The 3D memory device according to claim 10 , wherein the CMOS wafer includes a second substrate for forming HV circuits of the page buffers and the low-voltage (LV) circuitry and low-low-voltage (LLV) circuitry of the plurality of peripheral devices.
  12. 12 . The 3D memory device according to claim 3 , wherein the 3D memory device further comprises: an insulating layer formed over the second substrate; at least one through substrate contact penetrating the second substrate; and at least one array pad in contact with the at least one through substrate contact.
  13. 13 . The 3D memory device according to claim 4 , wherein the CMOS layer is formed based on a peripheral-under-chip (PUC) mechanism, and the CMOS layer is located under the memory array layer and separated by a base layer for forming the memory array layer.
  14. 14 . The 3D memory device according to claim 13 , wherein the base layer is a polysilicon layer, the array wafer includes a first substrate, the CMOS layer comprises a device layer formed on the first substrate, the polysilicon layer is formed on the device layer of the CMOS layer, and the memory array layer is formed on the polysilicon layer.
  15. 15 . The 3D memory device according to claim 14 , wherein the CMOS wafer includes a second substrate for forming HV circuits of the page buffers and the low-voltage (LV) circuitry and low-low-voltage (LLV) circuitry of the plurality of peripheral devices.
  16. 16 . The 3D memory device according to claim 4 , wherein the 3D memory device further comprises: an insulating layer formed over the second substrate; at least one through substrate contact penetrating the second substrate; and at least one array pad in contact with the at least one through substrate contact.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application claims the priority to Chinese Patent Application No. 202211585233.3, filed on Dec. 9, 2022, the content of which is incorporated herein by reference in its entirety. FIELD OF THE DISCLOSURE The present disclosure generally relates to the field of memory device and, more particularly, relates to a memory device structure and fabrication method thereof. BACKGROUND Planar memory cells are scaled to smaller sizes by improving process technology, circuit design, programming algorithm, and fabrication process. However, as feature sizes of the memory cells approach a lower limit, planar process and fabrication techniques become challenging and costly. As a result, memory density for planar memory cells approaches an upper limit. 3D memory architecture can address the density limitation in planar memory cells. 3D memory architecture includes a memory array and peripheral devices for controlling signals to and from the memory array. For 3D NAND memory devices, the peripheral devices are often located in a complementary metal-oxide-semiconductor (CMOS) area. As the number of 3D NAND layers continues to increase, the memory array size under the same capacity continues to decrease, which also requires the CMOS area to continue to shrink. Often more than one CMOS areas are used. Such requirement is often challenging when designing and fabricating the 3D NAND memory devices. The disclosed devices and fabrication methods are directed to solve one or more problems set forth above and other problems in the art. BRIEF SUMMARY OF THE DISCLOSURE One aspect of the present disclosure provides a method for forming a 3D memory device. The method includes forming an array wafer having a memory array layer and a CMOS layer stacked together, including: forming the CMOS layer having HV circuitry of a plurality of peripheral devices, and forming a plurality of memory cells and a stair structure in the memory array layer. The memory array layer includes at least one cell region for forming the memory cells and at least one stair structure region for forming the stair structure, and the CMOS layer includes at least one string driver region. The method also includes forming a CMOS wafer having LV circuitry and LLV circuitry of the plurality of peripheral devices, wherein the CMOS wafer includes at least one page buffer region; bonding the array wafer and the CMOS wafer at a bonding interface; and forming the 3D memory device based on the bonded array wafer and CMOS wafer. Another aspect of the present disclosure provides a 3D memory device. The 3D memory device includes an array wafer having a memory array layer and a CMOS layer stacked together. The CMOS layer has HV circuitry of a plurality of peripheral devices, and the memory array layer has a plurality of memory cells and a stair structure. The memory array layer includes at least one cell region for forming the memory cells and at least one stair structure region for forming the stair structure, and the CMOS layer includes at least one string driver region. The 3D memory device also includes a CMOS wafer having LV circuitry and LLV circuitry of the plurality of peripheral devices. The CMOS wafer includes at least one page buffer region, and the array wafer and the CMOS wafer are bonded at a bonding interface. Another aspect of the present disclosure provides a memory system. The memory system includes a 3D memory device, a memory controller coupled to the 3D memory device for controlling the 3D memory device; and an external interface for communicating with a host for storing information in the 3D memory device. The 3D memory device includes an array wafer having a memory array layer and a CMOS layer stacked together. The CMOS layer has HV circuitry of a plurality of peripheral devices, and the memory array layer has a plurality of memory cells and a stair structure. The memory array layer includes at least one cell region for forming the memory cells and at least one stair structure region for forming the stair structure, and the CMOS layer includes at least one string driver region. The 3D memory device also includes a CMOS wafer having LV circuitry and LLV circuitry of the plurality of peripheral devices. The CMOS wafer includes at least one page buffer region, and the array wafer and the CMOS wafer are bonded at a bonding interface. Other aspects of the present disclosure can be understood by those skilled in the art in light of the description, the claims, and the drawings of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS The following drawings are merely examples for illustrative purposes according to various disclosed embodiments and are not intended to limit the scope of the present disclosure. FIG. 1A illustrates a block diagram of a 3D memory device consistent with various disclosed embodiments in the present disclosure; FIG. 1B illustrates certain devices included in the peripheral circuitry of a 3D memor