US-12626763-B2 - Three-dimensional flash memory including floating devices, and manufacturing method therefor

Abstract

A three-dimensional flash memory including floating devices and a manufacturing method therefor are disclosed. A method for manufacturing a three-dimensional flash memory according to an embodiment may comprise the steps of: preparing a semiconductor structure including a plurality of word lines and a plurality of interlayer insulating layers, which are alternately stacked in a vertical direction while extending in a horizontal direction, respectively, and at least one memory cell string formed extending through the plurality of word lines and the plurality of interlayer insulating layers in the vertical direction, wherein the at least one memory cell string constitutes a plurality of memory cells corresponding to the plurality of word lines, while including a channel layer formed extending in the vertical direction, a charge storage layer formed to surround the channel layer, and a floating device layer formed extending to surround the charge storage layer; removing the plurality of interlayer insulating layers from the semiconductor structure; and removing regions of the floating device layer corresponding to the plurality of interlayer insulating layers, in order to form a plurality of floating devices isolated from each other.

Inventors

• Yun Heub Song

Assignees

• IUCF-HYU (INDUSTRY UNIVERSITY COOPERATION FOUNDATION HANYANG UNIVERSITY)

Dates

Publication Date

20260512

Application Date

20211126

Priority Date

20210217

Claims (5)

1. 1 . A method of manufacturing a three-dimensional (3D) flash memory including a floating device, the method comprising: preparing a semiconductor structure including a plurality of word lines and a plurality of interlayer insulating layers that are alternately stacked in a vertical direction while each extending in a horizontal direction, at least one memory cell string that is formed extending by passing through the plurality of word lines and the plurality of interlayer insulating layers in the vertical direction, the at least one memory cell string constituting a plurality of memory cells corresponding to the plurality of word lines while including a channel layer formed extending in the vertical direction, a charge storage layer formed to surround the channel layer, and a floating device layer formed extending to surround the charge storage layer; removing the plurality of interlayer insulating layers from the semiconductor structure; and removing regions corresponding to the plurality of interlayer insulating layers in the floating device layer to form a plurality of floating devices isolated from each other.
2. 2 . The method of claim 1 , wherein the removing the regions corresponding to the plurality of interlayer insulating layers in the floating device layer comprises removing the regions corresponding to the plurality of interlayer insulating layers in the floating device layer through a plurality of air gaps that are spaces in which the plurality of interlayer insulating layers are removed.
3. 3 . The method of claim 1 , wherein the removing the regions corresponding to the plurality of interlayer insulating layers in the floating device layer comprises removing the regions corresponding to the plurality of interlayer insulating layers in the floating device layer using a thermal oxidation process.
4. 4 . The method of claim 1 , wherein the removing the plurality of interlayer insulating layers and the removing the regions corresponding to the plurality of interlayer insulating layers in the floating device layer is performed through a single process.
5. 5 . The method of claim 1 , further comprising: forming a floating gate oxide layer in spaces in which regions corresponding to the plurality of interlayer insulating layers in the floating device layer are removed to isolate the plurality of memory cells from each other.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application is a National Stage of International Application No. PCT/KR2021/017624, filed Nov. 26, 2021, which claims the benefit of Korean Application No. 10-2021-0021345, filed Feb. 17, 2021, the disclosures of which are hereby incorporated by reference in their entirety. TECHNICAL FIELD The following example embodiments relate to a three-dimensional (3D) flash memory, and more particularly, to technology for a 3D flash memory including a floating device and a manufacturing method thereof. RELATED ART A flash memory device refers to an electrically erasable programmable read only memory (EEPROM) and the memory may be commonly used for, for example, a computer, a digital camera, an MP3 player, a game system, and a memory stick. The flash memory device electrically controls input and output of data through Fowler-Nordheim (F-N) tunneling or hot electron injection. In detail, referring to FIG. 1 that illustrates an array of a conventional three-dimensional (3D) flash memory, the array of the 3D flash memory may include a common source line (CSL), a bit line (BL), and a plurality of cell strings (CSTRs) provided between the common source line (CSL) and the bit line (BL). The bit lines are two-dimensionally arranged and the plurality of cell strings (CSTRs) are connected in parallel to each of the bit lines. The cell strings (CSTRs) may be commonly connected to the common source line (CSL). That is, the plurality of cell strings (CSTRs) may be provided between the plurality of bit lines and a single common source line (CSL). Here, a plurality of common source lines (CSLs) may be present and the plurality of common source lines (CSLs) may be two-dimensionally arranged. Here, the same voltage may be electrically applied to the plurality of common source lines (CSLs), or each of the plurality of common source lines (CSLs) may be electrically controlled. Each of the cell strings (CSTRs) may include a ground selection transistor (GST) configured to connect to the common source line (CSL), a string selection transistor (SST) configured to connect to the bit line (BL), and a plurality of memory cell transistors (MCTs) provided between ground and string selection transistors (GST and SST). The ground selection transistor (GST), the string selection transistor (SST), and the memory cell transistors (MCT) may be connected in series. The common source line (CSL) may be commonly connected to sources of the ground selection transistors (GSTs). In addition thereto, the ground selection line (GSL), the plurality of word lines (WL0-WL3), and the plurality of string selection lines (SSLs) provided between the common source line (CSL) and the bit line (BL) may be used as electrode layers of the ground selection transistor (GST), the memory cell transistors (MCTs), and the string selection transistors (SSTs), respectively. Also, each of the memory cell transistors (MCTs) includes a memory element. Meanwhile, the conventional 3D flash memory increases degree of integration by vertically stacking cells to meet excellent performance and low prices requested by consumers. For example, referring to FIG. 2 that illustrates a structure of a conventional 3D flash memory, the conventional 3D flash memory is manufactured by providing an electrode structure 215 in which interlayer insulating layers 211 and horizontal structures 250 are alternately and repeatedly formed on a substrate 200. The interlayer insulating layers 211 and the horizontal structures 250 may extend in a first direction. The interlayer insulating layers 211 may be, for example, silicon oxide films and, among the interlayer insulating layers 211, a bottom interlayer insulating layer 211a may have a thickness less than those of the remaining interlayer insulating layers 211. Each of the horizontal structures 250 may include first and second blocking insulating films 242 and 243 and an electrode layer 245. A plurality of electrode structures 215 may be provided and the plurality of electrode structures 215 may be provided to face each other in a second direction that crosses the first direction. The first direction and the second direction may correspond to the x-axis and the y-axis of FIG. 2, respectively. Trenches 240 configured to isolate the plurality of electrode structures 215 from each other may extend in the first direction between the plurality of electrode structures 215. Highly doped impurity regions may be formed in the substrate 200 exposed by the trenches 240 and the common source line (CSL) may be provided. Although not illustrated, separation insulating films that fill the trenches 240 may be further provided. Vertical structures 230 that pass through the electrode structure 215 may be provided. For example, the vertical structures 230 may be aligned in a matrix form along the first direction and the section direction from a planar perspective. As another example, the vertical structures 230 may be aligned in the