US-12626764-B2 - Semiconductor memory device and method of manufacturing semiconductor memory device

US12626764B2US 12626764 B2US12626764 B2US 12626764B2US-12626764-B2

Abstract

A semiconductor memory device includes a first stacked body, a second stacked body, an interposed portion, and a columnar body. The interposed portion is disposed between the first stacked body and the second stacked body. The columnar body includes a first columnar portion extending in a first direction inside the first stacked body, a second columnar portion extending in the first direction inside the second stacked body, and a connection portion disposed in the interposed portion and connecting the first columnar portion to the second columnar portion. At least part of the interposed portion has a first layer containing a first insulating material, a second layer disposed between the first layer and the second stacked body in the first direction and containing the first insulating material, and a third layer disposed between the first layer and the second layer in the first direction and containing a first material different from the first insulating material.

Inventors

Satoshi Nagashima

Assignees

KIOXIA CORPORATION

Dates

Publication Date: 20260512
Application Date: 20230901
Priority Date: 20220920

Claims (20)

1 . A semiconductor memory device comprising: a first stacked body disposed in a first region and a second region when viewed from a first direction, the first stacked body including a plurality of first gate electrode layers and a plurality of first insulating layers alternately stacked one by one in the first direction; a second stacked body disposed at a position different from a position of the first stacked body in the first direction, the second stacked body including a plurality of second gate electrode layers and a plurality of second insulating layers alternately stacked one by one in the first direction; an interposed portion disposed between the first stacked body and the second stacked body in the first direction; a columnar body having a channel layer and a memory film, the columnar body including a first columnar portion, a second columnar portion and a connection portion, the first columnar portion extending in the first direction inside the first stacked body, the second columnar portion extending in the first direction inside the second stacked body, and the connection portion disposed in the interposed portion, having a step, and connecting the first columnar portion to the second columnar portion, the step having different widths in a second direction intersecting the first direction between the connection portion and the second columnar portion, and is disposed in the first region; a first contact disposed in the second region, in contact with one of the plurality of first gate electrode layers, and extending in the first direction; and a second contact disposed in the second region, in contact with one of the plurality of second gate electrode layers, and extending in the first direction, wherein the interposed portion having a thickness in the first direction larger than a thickness of the first insulating layer in both the first region and the second region, and at least a part of the interposed portion has a first layer containing a first insulating material, a second layer disposed between the first layer and the second stacked body in the first direction and containing the first insulating material, and a third layer disposed between the first layer and the second layer in the first direction and containing a first material different from the first insulating material.
2 . The semiconductor memory device according to claim 1 , wherein the first material is a second insulating material different from the first insulating material.
3 . The semiconductor memory device according to claim 2 , wherein the second insulating material is an insulating material that has characteristics closer to silicon nitride than the first insulating material with respect to a first etchant, and has characteristics closer to the first insulating material than the silicon nitride with respect to a second etchant, the second etchant being different from the first etchant.
4 . The semiconductor memory device according to claim 3 , wherein the first etchant is an etchant containing carbon and fluorine, and the second etchant is an etchant containing phosphoric acid.
5 . The semiconductor memory device according to claim 2 , wherein the first insulating material contains oxygen, and the second insulating material contains nitrogen.
6 . The semiconductor memory device according to claim 5 , wherein the second insulating material contains carbon and nitrogen.
7 . The semiconductor memory device according to claim 1 , wherein the first material is a metal material.
8 . The semiconductor memory device according to claim 7 , wherein the metal material is the same as a metal material contained in the plurality of first gate electrode layers.
9 . The semiconductor memory device according to claim 7 , further comprising: a contact disposed in the second region, extending in the first direction, and being in contact with the third layer.
10 . The semiconductor memory device according to claim 1 , wherein the third layer is provided over the first region and the second region.
11 . The semiconductor memory device according to claim 1 , wherein the interposed portion has a first portion located in the first region and a second portion located in the second region, the second portion includes the first layer, the second layer, and the third layer, and the first portion is made of the first insulating material.
12 . The semiconductor memory device according to claim 1 , wherein when viewed from the first direction, an end of the third layer in the second direction is located between (i) an end of one first gate electrode layer in the second direction among the plurality of first gate electrode layers and (ii) an end of one second gate electrode layer in the second direction among the plurality of second gate electrode layers.
13 . The semiconductor memory device according to claim 1 , wherein the second region further includes a plurality of contacts that penetrate through the third layer in the first direction and into the first stacked body.
14 . The semiconductor memory device according to claim 1 , wherein at least part of the interposed portion has a fourth layer disposed between the second layer and the second stacked body in the first direction, the fourth layer containing the first insulating material, and a fifth layer disposed between the second layer and the fourth layer in the first direction, the fifth layer containing the first material.
15 . A method of manufacturing a semiconductor memory device, the method comprising: forming a stacked body including a first stacked body, a second stacked body, and an interposed portion, in which in the first stacked body, a plurality of first films and a plurality of second films are alternately stacked one by one in a first direction, the second stacked body is disposed at a position different from a position of the first stacked body in the first direction, and includes a plurality of third films and a plurality of fourth films alternately stacked one by one in the first direction, the interposed portion is disposed between the first stacked body and the second stacked body in the first direction, and at least a part of the interposed portion has a first layer containing: a first insulating material, a second layer disposed between the first layer and the second stacked body in the first direction and containing the first insulating material, and a third layer disposed between the first layer and the second layer in the first direction and containing a first material different from the first insulating material; and collectively processing a first space portion reaching the third layer and a second space portion having a depth in the first direction larger than a depth of the first space portion and reaching one first film among the plurality of first films.
16 . The method according to claim 15 , wherein the first material is a second insulating material different from the first insulating material.
17 . The method according to claim 16 , wherein the second insulating material is an insulating material that has characteristics closer to silicon nitride than the first insulating material with respect to a first etchant, and has characteristics closer to the first insulating material than the silicon nitride with respect to a second etchant, the second etchant being different from the first etchant.
18 . The method according to claim 17 , wherein the first etchant is an etchant containing carbon and fluorine, and the second etchant is an etchant containing phosphoric acid.
19 . The method according to claim 16 , wherein the first insulating material contains oxygen, and the second insulating material contains nitrogen.
20 . The method according to claim 19 , wherein the second insulating material contains carbon and nitrogen.

Description

CROSS-REFERENCE TO RELATED APPLICATION(S) This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2022-149186, filed Sep. 20, 2022, the entire contents of which are incorporated herein by reference. FIELD Embodiments described herein relate generally to a semiconductor memory device and a method of manufacturing a semiconductor memory device. BACKGROUND There is a semiconductor memory device that has a stacked body in which word lines and insulating layers are alternately stacked, and a memory pillar penetrating through the stacked body. DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a configuration of a semiconductor memory device according to a first embodiment. FIG. 2 is a diagram showing an equivalent circuit of a part of a memory cell array of the first embodiment. FIG. 3 is a sectional view showing a part of the memory cell array of the first embodiment. FIG. 4 is a sectional view along the line IV-IV of a part of the memory cell array shown in FIG. 3. FIG. 5 is a sectional view showing a region surrounded by the line F5 of the memory cell array shown in FIG. 4. FIG. 6 is a sectional view along the line VI-VI of the memory cell array shown in FIG. 5. FIG. 7 is a sectional view showing a region surrounded by the line F7 of the memory cell array shown in FIG. 3. FIG. 8 is a sectional view showing a staircase region forming step according to the first embodiment. FIG. 9 is a sectional view showing the staircase region forming step according to the first embodiment. FIG. 10 is a sectional view showing the staircase region forming step according to the first embodiment. FIG. 11 is a sectional view showing the method of manufacturing the semiconductor memory device of the first embodiment. FIG. 12 is a sectional view showing the method of manufacturing the semiconductor memory device of the first embodiment. FIG. 13 is a sectional view showing the method of manufacturing the semiconductor memory device of the first embodiment. FIG. 14 is a sectional view showing the method of manufacturing the semiconductor memory device of the first embodiment. FIG. 15 is a sectional view showing the details of a step relating to a first hole of the first embodiment. FIG. 16 is a sectional view showing a part of a semiconductor memory device according to a second embodiment. FIG. 17 is a sectional view showing a method of manufacturing the semiconductor memory device according to the second embodiment. FIG. 18 is a sectional view showing the method of manufacturing the semiconductor memory device according to the second embodiment. FIG. 19 is a sectional view showing the method of manufacturing the semiconductor memory device according to the second embodiment. FIG. 20 is a sectional view showing the method of manufacturing the semiconductor memory device according to the second embodiment. FIG. 21 is a sectional view showing the method of manufacturing the semiconductor memory device according to the second embodiment. FIG. 22 is a sectional view showing the method of manufacturing the semiconductor memory device according to the second embodiment. FIG. 23 is a sectional view showing a part of a semiconductor memory device according to a third embodiment. FIG. 24 is a sectional view showing a method of manufacturing a semiconductor memory device according to the third embodiment. FIG. 25 is a sectional view showing the method of manufacturing a semiconductor memory device according to the third embodiment. FIG. 26 is a sectional view showing the method of manufacturing a semiconductor memory device according to the third embodiment. FIG. 27 is a sectional view showing a part of a semiconductor memory device according to a fourth embodiment. FIG. 28 is a sectional view showing a method of manufacturing the semiconductor memory device according to the fourth embodiment. FIG. 29 is a sectional view showing the method of manufacturing the semiconductor memory device according to the fourth embodiment. FIG. 30 is a sectional view showing a part of a semiconductor memory device according to a first modification example of the embodiment. FIG. 31 is a sectional view showing a part of a semiconductor memory device according to a second modification example of the embodiment. FIG. 32 is a sectional view showing a part of a semiconductor memory device according to a third modification example of the embodiment. FIG. 33 is a sectional view along the line XXXIII-XXXIII of the semiconductor memory device shown in FIG. 32. FIG. 34 is a sectional view along the line XXXIV-XXXIV of the semiconductor memory device shown in FIG. 32. DETAILED DESCRIPTION Embodiments provide a semiconductor memory device and a method of manufacturing a semiconductor memory device that can improve manufacturability. In general, according to at least one embodiment, a semiconductor memory device has a first stacked body, a second stacked body, an interposed portion, a columnar body, a first contact,