US-12626765-B2 - Nonvolatile memory devices and methods of controlling wordline erase operations within sub-blocks of memory strings

Abstract

A nonvolatile memory device may include at least one memory block and a control circuit. The at least one memory block includes a plurality of cell strings that are divided into a plurality of sub-blocks arranged in the vertical direction, and each of the sub-blocks includes boundary word-lines adjacent to another sub-block and internal word-lines different from the boundary word-lines. The control circuit may be configured to control an erase operation by applying a pre-program voltage with a first individual bias condition sequentially to the internal word-lines and the at least one boundary word-line of at least one sub-block to be erased from among the plurality of sub-blocks during a pre-program period of an erase loop, and by applying an erase voltage to a channel of the at least one memory block during an erase execution period of the erase loop.

Inventors

• Sangwon Park
• Jooyong Park
• Jaeha Park

Assignees

• SAMSUNG ELECTRONICS CO., LTD.

Dates

Publication Date

20260512

Application Date

20231117

Priority Date

20230613

Claims (20)

1. 1 . A nonvolatile memory device comprising: at least one memory block including a plurality of cell strings, each of the plurality of cell strings including: a string selection transistor, a plurality of memory cells and a ground selection transistor which are connected in series and arranged in a vertical direction between a bit-line and a common source line, wherein the at least one memory block is divided into a plurality of sub-blocks arranged in the vertical direction, and wherein each of the plurality of sub-blocks includes at least one boundary word-line adjacent to another sub-block of the plurality of sub-blocks and internal word-lines different from the at least one boundary word-line; and a control circuit configured to control an erase operation by: applying a pre-program voltage with a first individual bias condition sequentially to the internal word-lines and the at least one boundary word-line of at least one sub-block to be erased from among the plurality of sub-blocks during a pre-program period of an erase loop, wherein the internal word-lines and the at least one boundary word-line are coupled to multi-level memory cells of the plurality of memory cells, which are configured to store data; and applying an erase voltage to a channel of the at least one memory block during an erase execution period of the erase loop.
2. 2 . The nonvolatile memory device of claim 1 , further comprising: a voltage generator configured to generate, based on a control signal, word-line voltages including the pre-program voltage and the erase voltage; and an address decoder configured to provide the word-line voltages to the at least one memory block based on a row address, and wherein the control circuit is configured to control the voltage generator and the address decoder based on a command and an address including the row address.
3. 3 . The nonvolatile memory device of claim 2 , wherein the control circuit is configured to control the voltage generator and the address decoder to: during a first sub-period of the pre-program period: apply a first pre-program voltage to the internal word-lines of the at least one sub-block to be erased; and apply a pass voltage to word-lines of at least one sub-block not to be erased from among the plurality of sub-blocks, and during a second sub-period of the pre-program period: apply a second pre-program voltage to the at least one boundary word-line of the at least one sub-block to be erased; and apply the pass voltage to the word-lines of the at least one sub-block not to be erased.
4. 4 . The nonvolatile memory device of claim 3 , wherein the control circuit is further configured to control the voltage generator and the address decoder to: apply the first pre-program voltage during the first sub-period; and apply the second pre-program voltage during the second sub-period, the second sub-period having a time interval different from a time interval of the first sub-period.
5. 5 . The nonvolatile memory device of claim 3 , wherein the control circuit is further configured to control the voltage generator and the address decoder to: apply the first pre-program voltage during the first sub-period; and apply the second pre-program voltage during the second sub-period, the second pre-program voltage having a voltage level that is different from a voltage level of the first pre-program voltage.
6. 6 . The nonvolatile memory device of claim 3 , wherein the control circuit is further configured to control the voltage generator and the address decoder to: apply a word-line erase voltage to the internal word-lines and the at least one boundary word-line of the at least one sub-block to be erased during the erase execution period; and float the word-lines of the at least one sub-block not to be erased.
7. 7 . The nonvolatile memory device of claim 2 , wherein the control circuit is further configured to control the erase operation by: applying an erase verification voltage with a second individual bias condition sequentially to the internal word-lines and the at least one boundary word-line of the at least one sub-block to be erased during an erase verification period of the erase loop successive to the erase execution period.
8. 8 . The nonvolatile memory device of claim 7 , wherein the word-line voltages further include the erase verification voltage; and wherein the control circuit is further configured to control the voltage generator and the address decoder to: apply a first erase verification voltage to the at least one boundary word-line of the at least one sub-block to be erased during a first sub-period of the erase verification period; apply a second erase verification voltage to the internal word-lines of the at least one sub-block to be erased during a second sub-period of the erase verification period; and apply a read voltage to the word-lines of at least one sub-block not to be erased from among a plurality of sub-blocks during each of the first sub-period and the second sub-period.
9. 9 . The nonvolatile memory device of claim 8 , wherein the control circuit is further configured to control the voltage generator and the address decoder to: apply the first erase verification voltage during the first sub-period; and apply the second erase verification voltage during the second sub-period, the second sub-period having a time interval different from a time interval of the first sub-period.
10. 10 . The nonvolatile memory device of claim 8 , wherein the control circuit is further configured to control the voltage generator and the address decoder to: apply the first erase verification voltage during the first sub-period; and apply the second erase verification voltage during the second sub-period, the second sub-period having a voltage level different from a voltage level of the first erase verification voltage.
11. 11 . The nonvolatile memory device of claim 2 , wherein the plurality of sub-blocks include a first sub-block, a second sub-block and a third sub-block stacked in the vertical direction from the common source line, and wherein the control circuit is further configured to select one of the first sub-block, the second sub-block and the third sub-block as the at least one sub-block to be erased.
12. 12 . The nonvolatile memory device of claim 2 , wherein the plurality of sub-blocks include a first sub-block, a second sub-block and a third sub-block stacked in the vertical direction from the common source line, and wherein the control circuit is configured to select the first sub-block and the third sub-block that are not adjacent to each other as the at least one sub-block to be erased.
13. 13 . The nonvolatile memory device of claim 12 , wherein the control circuit is configured to control the voltage generator and the address decoder to: during a first sub-period of the pre-program period: apply a first pre-program voltage to boundary word-lines of each of the first sub-block and the third sub-block; and apply a pass voltage to word-lines of the second sub-block, during a second sub-period of the pre-program period: apply a second pre-program voltage to internal word-lines of each of the first sub-block and the third sub-block; and apply the pass voltage to the word-lines of the second sub-block, and during the erase execution period: apply a word-line erase voltage to the boundary word-lines and the internal word-lines of each of the first sub-block and the third sub-block; and float the word-lines of the second sub-block.
14. 14 . The nonvolatile memory device of claim 12 , wherein the control circuit is further configured to control the voltage generator and the address decoder to: during a first sub-period of an erase verification period of the erase loop successive to the erase execution period: apply a first erase verification voltage to first and second boundary word-lines of each of the first sub-block and the third sub-block; apply a read voltage to internal word-lines of each of the first sub-block and the third sub-block; and apply the read voltage to word-lines of the second sub-block, and during a second sub-period of the erase verification period of the erase loop: apply a second erase verification voltage to the internal word-lines of each of the first sub-block and the third sub-block; apply the read voltage to the first and second boundary word-lines of each of the first sub-block and the third sub-block; and apply the read voltage to the word-lines of the second sub-block.
15. 15 . The nonvolatile memory device of claim 2 , wherein the plurality of sub-blocks include a first sub-block, a second sub-block and a third sub-block stacked in the vertical direction from the common source line, and wherein the control circuit is configured to select the first sub-block and the second sub-block that are adjacent to each other as the at least one sub-block to be erased.
16. 16 . The nonvolatile memory device of claim 15 , wherein the control circuit is further configured to control the voltage generator and the address decoder to: during a first sub-period of the pre-program period: apply a first pre-program voltage to internal word-lines and non-adjacent boundary word-lines of each of the first sub-block and the second sub-block; and apply a pass voltage to word-lines of the third sub-block, during a second sub-period of the pre-program period: apply a second pre-program voltage to the non-adjacent boundary word-lines of each of the first sub-block and the second sub-block; and apply the pass voltage to the word-lines of the third sub-block and adjacent boundary word-lines of each of the first sub-block and the second sub-block; and during the erase execution period: apply a word-line erase voltage to boundary word-lines and the internal word-lines of each of the first sub-block and the second sub-block; and float the word-lines of the third sub-block.
17. 17 . The nonvolatile memory device of claim 15 , wherein the control circuit is further configured to control the voltage generator and the address decoder to: during a first sub-period of an erase verification period of the erase loop successive to the erase execution period: apply a first erase verification voltage to non-adjacent boundary word-lines of each of the first sub-block and the second sub-block; apply a read voltage to internal word-lines and adjacent boundary word-lines of each of the first sub-block and the second sub-block; and apply the read voltage to word-lines of the third sub-block, and during a second sub-period of the erase verification period of the erase loop: apply a second erase verification voltage to the internal word-lines and the non-adjacent word-lines of each of the first sub-block and the second sub-block; apply the read voltage to the adjacent boundary word-lines of each of the first sub-block and the second sub-block; and apply the read voltage to the word-lines of the third sub-block.
18. 18 . A method of controlling an erase operation of a nonvolatile memory device, the method comprising: dividing at least one memory block including a plurality of cell strings into a plurality of sub-blocks arranged in a vertical direction, each of the plurality of cell strings including: a string selection transistor, a plurality of memory cells and a ground selection transistor which are connected in series and arranged in the vertical direction between a bit-line and a common source line, wherein each of the plurality of sub-blocks includes at least one boundary word-line that is adjacent to another sub-block of the plurality of sub-blocks, and wherein each of the plurality of sub-blocks includes internal word-lines different from the at least one boundary word-line; applying a pre-program voltage with a first individual bias condition sequentially to the internal word-lines and the at least one boundary word-line of at least one sub-block to be erased from among the plurality of sub-blocks during a pre-program period of an erase loop, wherein the internal word-lines and the at least one boundary word-line are coupled to multi-level memory cells of the plurality of memory cells, which are configured to store data; and applying an erase voltage to a channel of the at least one memory block during an erase execution period of the erase loop.
19. 19 . The method of claim 18 , further comprising: applying an erase verification voltage with a second individual bias condition sequentially to the internal word-lines and the at least one boundary word-line of the at least one sub-block to be erased during an erase verification period of the erase loop successive to the erase execution period.
20. 20 . A nonvolatile memory device comprising: at least one memory block including a plurality of cell strings, each of the plurality of cell strings including: a string selection transistor, a plurality of memory cells and a ground selection transistor which are connected in series and arranged in a vertical direction between a source line and a bit-line, wherein the at least one memory block is divided into a plurality of sub-blocks arranged in the vertical direction, with each of the plurality of sub-blocks including at least one boundary word-line that is adjacent to another sub-block and each of the plurality of sub-blocks including internal word-lines different from the at least one boundary word-line; and a control circuit configured to control an erase operation by: applying a pre-program voltage to word-lines of at least one sub-block to be erased from among the plurality of sub-blocks during a pre-program period of an erase loop, wherein the word-lines of the at least one sub-block are coupled to multi-level memory cells of the plurality of memory cells, which are configured to store data; applying an erase voltage to a channel of the at least one memory block during an erase execution period of the erase loop; and applying an erase verification voltage to at least one boundary word-line of the at least one sub-block to be erased during an erase verification period of the erase loop.

Description

CROSS-REFERENCE TO RELATED APPLICATION This US application claims priority under 35 USC § 119 to Korean Patent Application No. 10-2023-0075261, filed on Jun. 13, 2023, in the Korean Intellectual Property Office (KIPO), and the entire contents of the above-identified application are incorporated by reference herein. BACKGROUND 1. Technical Field Aspects of the present disclosure generally relate to semiconductor memory devices, and more particularly to nonvolatile memory devices and to methods of controlling erase operations of nonvolatile memory devices. 2. Discussion of the Related Art Semiconductor memory devices for storing data may be classified into volatile memory devices and nonvolatile memory devices. Volatile memory devices, such as dynamic random access memory (DRAM) devices, are typically configured to store data by charging or discharging capacitors in memory cells, and lose the stored data when power is turned off or disconnected therefrom. Nonvolatile memory devices, such as flash memory devices, may maintain stored data even when power is turned off or disconnected. Volatile memory devices are widely used as main memories of various apparatuses, while nonvolatile memory devices are widely used for storing program codes and/or data in various electronic devices, such as computers, mobile devices, etc. Recently, nonvolatile memory devices of three-dimensional structure such as a vertical NAND memory devices have been developed to increase integration degree and memory capacity of the nonvolatile memory devices. Along with increases in the integration degree and memory capacity, characteristics of word-lines (e.g., boundary word-lines) may be degraded when an erase operation of the nonvolatile memory device is performed. SUMMARY Some example embodiments may provide nonvolatile memory devices capable of enhancing a characteristic of boundary word-lines. Some example embodiments may provide methods of controlling erase operations of nonvolatile memory devices, capable of enhancing a characteristic of a boundary word-line. According to some example embodiments, a nonvolatile memory device is provided, where the nonvolatile memory device may include at least one memory block and a control circuit. The at least one memory block may include a plurality of cell strings, where each of the plurality of cell strings includes a string selection transistor, a plurality of memory cells, and a ground selection transistor which are connected in series and arranged in a vertical direction between a bit-line and a common source line. The at least one memory block may be divided into a plurality of sub-blocks that may be arranged in the vertical direction. Each of the plurality of sub-blocks includes at least one boundary word-line adjacent to another sub-block of the plurality of sub-blocks, and internal word-lines different from at least one boundary word-line. The control circuit may be configured to control an erase operation by applying a pre-program voltage with a first individual bias condition sequentially to the internal word-lines and the at least one boundary word-line of at least one sub-block to be erased from among the plurality of sub-blocks during a pre-program period of an erase loop, and by applying an erase voltage to a channel of the at least one memory block during an erase execution period of the erase loop. According to some example embodiments, a method of controlling an erase operation of a nonvolatile memory device is provided. According to the method, at least one memory block including a plurality of cell strings may be divided into a plurality of sub-blocks arranged in a vertical direction, where each of the plurality of cell strings includes a string selection transistor, a plurality of memory cells and a ground selection transistor which are connected in series and arranged in the vertical direction between a bit-line and a common source line. Each of the plurality of sub-blocks may include at least one boundary word-line adjacent to another sub-block of the plurality of sub-blocks, and internal word-lines different from at least one boundary word-line. A pre-program voltage with a first individual bias condition may be sequentially applied to the internal word-lines and the at least one boundary word-line of at least one sub-block to be erased from among the plurality of sub-blocks during a pre-program period of an erase loop, and an erase voltage may be applied to a channel of the at least one memory block during an erase execution period of the erase loop. According to some example embodiments, a nonvolatile memory device may be provided, where the nonvolatile memory device may include at least one memory block and a control circuit. The at least one memory block may include a plurality of cell strings, where each of the plurality of cell strings includes a string selection transistor, a plurality of memory cells and a ground selection transistor which are connected in series and