US-12626766-B2 - Method and apparatus for GIDL erase in memory systems

Abstract

The present disclosure relates to methods and devices for memory erase. In one example, a method for operating a memory device includes increasing a voltage of a source line (SL) coupled to a memory string from an initial voltage at a beginning of a time period, where the voltage of the SL is increased to an erase voltage at an end of the time period. The memory device can apply a first voltage to a first word line (WL) before the end of the time period. The memory device can apply a second voltage to a second WL adjacent to the first WL before the end of the time period. The memory device can further apply a third voltage to the second WL no later than the end of the time period, where the third voltage is higher than the second voltage.

Inventors

• Li Xiang
• Zhuo Chen

Assignees

• YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Dates

Publication Date

20260512

Application Date

20231122

Claims (20)

1. 1 . A method for operating a memory device, the method comprising: increasing a voltage of a source line (SL) coupled to a memory string from an initial voltage at a beginning of a time period, wherein the voltage of the SL is increased to an erase voltage at an end of the time period; applying a first voltage to a first word line (WL) before the end of the time period; applying a second voltage to a second WL adjacent to the first WL before the end of the time period; applying a third voltage to the second WL after applying the second voltage to the second WL but no later than the end of the time period, wherein the third voltage is higher than the second voltage; and in response to detecting that the voltage of the SL is increased to a release voltage during the time period, increasing a voltage of a gate of a first transistor comprised in the memory string to an offset voltage, the release voltage being smaller than the erase voltage, wherein memory cells coupled to the first WL are to be erased during an erase operation after the time period.
2. 2 . The method of claim 1 , wherein the first transistor is a bottom select gate (BSG) of the memory string, the BSG is coupled to a first terminal of a first driving transistor of a string driver, the first WL is coupled to a first terminal of a second driving transistor of the string driver, and the second WL is coupled to a first terminal of a third driving transistor of the string driver, and wherein the method further comprises: applying a string driver gate voltage to a gate of the first driving transistor, a gate of the second driving transistor, and a gate of the third driving transistor; increasing the string driver gate voltage from a supply voltage to a first string driver voltage before the end of the time period; and increasing the string driver gate voltage from the first string driver voltage to a second string driver voltage no later than the end of the time period.
3. 3 . The method of claim 1 , wherein the offset voltage is determined based on subtracting a threshold voltage of the first transistor from the first string driver voltage.
4. 4 . The method of claim 2 , wherein: providing a first voltage to the first WL comprises providing the first voltage to a second terminal of the second driving transistor; and providing a second voltage to the second WL comprises providing the second voltage to a second terminal of the third driving transistor.
5. 5 . The method of claim 2 , wherein the second string driver voltage is less than a sum of a threshold voltage of the BSG driver and a floating voltage of the BSG.
6. 6 . The method of claim 5 , wherein after the first transistor is floated, the floating voltage of the BSG increases as the voltage of the SL increases.
7. 7 . The method of claim 6 , wherein the memory string further comprises a top select gate (TSG) coupled to a bit line (BL), the BL is coupled to the SL through a switch, and the TSG is coupled to a first terminal of a fourth driving transistor of the string driver, and wherein the method further comprises: providing a voltage to a second terminal of the fourth driving transistor; and in response to detecting that a voltage of the BL is increased to a second release voltage, increasing the voltage of the second terminal of the fourth driving transistor.
8. 8 . The method of claim 1 , wherein the first WL and the second WL are associated with two consecutive index numbers, wherein the two consecutive index numbers are natural numbers.
9. 9 . The method of claim 1 , wherein the second WL is a dummy WL adjacent to the first WL.
10. 10 . A memory device comprising: a memory block comprising a bottom select gate (BSG), a source line (SL), a first word line (WL), a second WL, and a memory string comprising a channel coupled to the SL; and a peripheral circuit comprising a voltage generator, a string driver coupled to the BSG, the first WL, and the second WL, wherein the peripheral circuit is configured to: increase a voltage of the SL from an initial voltage at a beginning of a time period, wherein the voltage of the SL is increased to an erase voltage at an end of the time period; apply a first voltage to the first WL through the string driver before the end of the time period; apply a second voltage to the second WL through the string driver before the end of the time period; and apply a third voltage to the second WL through the string driver after applying the second voltage to the second WL but no later than the end of the time period, wherein the third voltage is higher than the second voltage, wherein the peripheral circuit is further configured to: increase a voltage of a gate of the BSG to an offset voltage to float the BSG in response to detecting that the voltage of the SL is increased to a release voltage during the time period, the release voltage being smaller than the erase voltage, wherein memory cells coupled to the first WL are to be erased during an erase operation after the time period.
11. 11 . The memory device of claim 10 , wherein a first driving transistor of the string driver is coupled to the BSG, a second driving transistor of the string driver is coupled to the first WL, a third driving transistor of the string driver is coupled to the second WL, gates of the first driving transistor, the second driving transistor, and the third driving transistor are coupled together, and wherein the voltage generator is further configured to: apply a string driver gate voltage to the gate of the first driving transistor; increase the string driver gate voltage from a supply voltage to a first string driver voltage after the beginning of the time period; and increase the string driver gate voltage from the first string driver voltage to a second string driver voltage no later than the end of the time period.
12. 12 . The memory device of claim 11 , wherein the first voltage is provided to a second terminal of the second driving transistor, and the second voltage is provided to a second terminal of the third driving transistor.
13. 13 . The memory device of claim 12 , wherein the second string driver voltage is less than an addition of a threshold voltage of the first driving transistor and a floating voltage of the BSG.
14. 14 . The memory device of claim 11 , wherein after the first transistor is floated, a floating voltage of the BSG increases as the voltage of the SL increases.
15. 15 . The memory device of claim 14 , wherein the memory block further comprises a bit line (BL) and a top select gate (TSG), the BL is coupled to the SL through a switch, and the TSG is coupled to a first terminal of a fourth driving transistor of the string driver, and wherein the voltage generator is further configured to: provide a voltage to a second terminal of the fourth driving transistor; and in response to detecting that a voltage of the BL is increased to a second release voltage, increase the voltage of the second terminal of the fourth driving transistor.
16. 16 . The memory device of claim 10 , wherein the first WL and the second WL are associated with two consecutive index numbers, wherein the two consecutive index numbers are natural numbers, and memory cells driven by the first WL are to be erased during a selective erase operation after the time period.
17. 17 . The memory device of claim 10 , wherein the second WL is a dummy WL adjacent to the first WL.
18. 18 . A memory system comprising a memory device and a memory controller, wherein: the memory controller is configured to control the memory device; and the memory device comprises: a memory block comprising a bottom select gate (BSG), a source line (SL), a first word line (WL), a second WL, and a memory string comprising a channel coupled to the SL, and a peripheral circuit comprising a voltage generator, a string driver coupled to the BSG, the first WL, and the second WL, wherein the peripheral circuit is configured to: increase a voltage of the SL from an initial voltage at a beginning of a time period, wherein the voltage of the SL is increased to an erase voltage at an end of the time period; apply a first voltage to the first WL through the string driver before the end of the time period; apply a second voltage to the second WL through the string driver before the end of the time period; and apply a third voltage to the second WL through the string driver after applying the second voltage to the second WL but no later than the end of the time period, wherein the third voltage is higher than the second voltage, wherein the peripheral circuit is further configured to: increase a voltage of a gate of the BSG to an offset voltage to float the BSG in response to detecting that the voltage of the SL is increased to a release voltage during the time period, the release voltage being smaller than the erase voltage, and wherein memory cells coupled to the first WL are to be erased during an erase operation after the time period.
19. 19 . The memory system of claim 18 , wherein a first driving transistor of the string driver is coupled to the BSG, a second driving transistor of the string driver is coupled to the first WL, a third driving transistor of the string driver is coupled to the second WL, gates of the first driving transistor, the second driving transistor, and the third driving transistor are coupled together, and wherein the voltage generator is further configured to: apply a string driver gate voltage to the gate of the first driving transistor; increase the string driver gate voltage from a supply voltage to a first string driver voltage after the beginning of the time period; and increase the string driver gate voltage from the first string driver voltage to a second string driver voltage no later than the end of the time period.
20. 20 . The memory system of claim 19 , wherein the first voltage is provided to a second terminal of the second driving transistor, and the second voltage is provided to a second terminal of the third driving transistor, and wherein the second string driver voltage is less than an addition of a threshold voltage of the first driving transistor and a floating voltage of the BSG.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application is a continuation of International Application No. PCT/CN2023/123724, filed on Oct. 10, 2023, the disclosure of which is hereby incorporated by reference in its entirety. TECHNICAL FIELD The present disclosure generally relates to memory devices and memory systems, and in particular, to memory cell erase operations. BACKGROUND Semiconductor memory devices can be categorized into volatile memory devices and non-volatile memory devices. The volatile memory devices lost data when power is off. The non-volatile memory devices can retain stored data when power is not connected. Flash memory is a low-cost and high-density non-volatile memory device, which includes NOR flash memory and NAND flash memory. Various operations, such as read, program (write), and erase, can be performed by the flash memory. SUMMARY The present disclosure relates to methods and devices for memory erase. In one example, a method for operating a memory device includes increasing a voltage of a source line (SL) coupled to a memory string from an initial voltage at a beginning of a time period, where the voltage of the SL is increased to an erase voltage at an end of the time period. The memory device can apply a first voltage to a first word line (WL) before the end of the time period. The memory device can apply a second voltage to a second WL adjacent to the first WL before the end of the time period. The memory device can further apply a third voltage to the second WL no later than the end of the time period, where the third voltage is higher than the second voltage. While generally described as computer-implemented software embodied on tangible media that processes and transforms the respective data, some or all of the aspects may be computer-implemented methods or further included in respective systems or other devices for performing this described functionality. The details of these and other aspects and implementations of the present disclosure are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the disclosure will be apparent from the description and drawings, and from the claims. BRIEF DESCRIPTION OF DRAWINGS FIG. 1 illustrates an example of a schematic diagram of a memory device including peripheral circuits, according to some aspects of the present disclosure. FIG. 2 illustrates an example of a side view of cross-sections of a memory cell array including NAND memory strings, according to some aspects of the present disclosure. FIG. 3 illustrates an example of a schematic diagram of some peripheral circuits, according to some aspects of the present disclosure. FIG. 4 illustrates an example of an example of gate induced drain leakage (GIDL) current generation in a memory string, according to some aspects of the present disclosure. FIG. 5 illustrates an example circuit for performing GIDL erase operations, according to some aspects of the present disclosure. FIG. 6 illustrates an example timing diagram of a GIDL erase operation, according to some aspects of the present disclosure. FIG. 7 illustrates an example timing diagram of another GIDL erase operation, according to some aspects of the present disclosure. FIG. 8 illustrates an example flowchart of a method for performing a GIDL erase operation, according to some aspects of the present disclosure. FIG. 9 illustrates a block diagram of an example system having a memory device, according to some aspects of the present disclosure. FIG. 10A illustrates a diagram of a memory card having a memory device, according to some aspects of the present disclosure. FIG. 10B illustrates a diagram of a solid-state drive (SSD) having a memory device, according to some aspects of the present disclosure. Like reference numbers and designations in the various drawings indicate like elements. DETAILED DESCRIPTION Gate induced drain leakage (GIDL) effect can be used in an erase operation of flash memory cells (e.g., NAND memory cells). GIDL occurs when a high voltage is applied to a drain of a metal-oxide-semiconductor field-effect transistor (MOSFET) transistor and a low voltage is applied to a gate of the transistor. In this situation, a depletion region is formed in an overlap region of the drain and the gate. Electron-hole pairs can be generated in the depletion region due to band-to-band tunneling. As a result, holes may flow from the drain to a substrate of the transistor, which creates a GIDL current. The GIDL current increases when increasing a voltage difference between the drain and the gate. In a GIDL erase operation of a flash memory device, a transistor (e.g., a bottom select gate (BSG)) of a memory string can serve as a GIDL generator. Specifically, a low voltage can be applied to a gate of the BSG, and a high voltage can be applied to a source line (SL) coupled to the BSG. A GIDL current can then be generated from the BSG, and holes can be injected into a channel of the