US-12626767-B2 - Memory devices, control methods of memory, and memory systems

US12626767B2US 12626767 B2US12626767 B2US 12626767B2US-12626767-B2

Abstract

The present application discloses a memory device, a control method of a memory device, and a memory system, and belongs to the technical field of memory device. The control method includes: a peripheral circuit receiving an erase instruction, and recording a number of the received erase instructions, wherein the erase instruction is to instruct the peripheral circuit to erase one memory block in a memory cell array; and the peripheral circuit, in response to the number of the received erase instructions reaching a number threshold, selecting one memory page in a first memory block of the memory cell array to perform program processing.

Inventors

Jialiang Deng
Yahai LIU
Yuankang YANG

Assignees

YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Dates

Publication Date: 20260512
Application Date: 20240903
Priority Date: 20240524

Claims (20)

1 . A method of operating a memory device, wherein the memory device includes a peripheral circuit and a memory cell array, and the method comprises, by the peripheral circuit: receiving an erase instruction, and recording a number of received erase instructions, wherein the erase instruction is to instruct the peripheral circuit to erase one memory block in the memory cell array; and in response to the number of the received erase instructions reaching a number threshold, selecting one memory page in a first memory block of the memory cell array to perform program processing, wherein the number threshold is equal to a total number of received erase instructions required for performing a preset number of program/erase cycles on each of second memory blocks in the memory cell array other than the first memory block, a number of memory pages in the first memory block that have been subjected to program processing is to indicate a number of program/erase cycles of the second memory blocks, and the preset number of program/erase cycles is equal to a ratio of a rated number of program/erase cycles corresponding to the second memory blocks to the number of memory pages in the first memory block.
2 . The method of claim 1 , wherein the peripheral circuit includes a plurality of registers, and the method further includes: determining the number of memory pages in the first memory block that have been subjected to program processing, and determining the number of program/erase cycles corresponding to the second memory blocks according to the number of memory pages that have been subjected to program processing; and writing the determined number of program/erase cycles to a first register in the plurality of registers.
3 . The method of claim 2 , wherein the peripheral circuit further includes an interface circuit, and the method further includes: receiving, by a query interface configured in the interface circuit, a query instruction for the number of program/erase cycles sent by a memory controller coupled with the memory device, and returning the number of program/erase cycles stored in the first register to the memory controller.
4 . The method of claim 2 , wherein determining the number of memory pages in the first memory block that have been subjected to program processing, and determining the number of program/erase cycles corresponding to the second memory blocks according to the number of memory pages that have been subjected to program processing includes: determining a target address corresponding to a memory page that has been subjected to program processing most recently among the number of memory pages that have been subjected to program processing; and determining the number of program/erase cycles corresponding to the target address according to a correspondence relationship between addresses and the number of program/erase cycles.
5 . The method of claim 2 , wherein determining the number of memory pages in the first memory block that have been subjected to program processing, and determining the number of program/erase cycles corresponding to the second memory blocks according to the number of memory pages that have been subjected to program processing includes: after the memory device is powered on, determining the number of memory pages in the first memory block that have been subjected to program processing, and determining the number of program/erase cycles corresponding to the second memory blocks according to the number of memory pages that have been subjected to program processing.
6 . The method of claim 5 , wherein after the memory device is powered on, determining the number of memory pages in the first memory block that have been subjected to program processing, and determining the number of program/erase cycles corresponding to the second memory blocks according to the number of memory pages that have been subjected to program processing includes: after the memory device is powered on, writing a first identification value to a second register in the plurality of registers, wherein the first identification value is to indicate that the memory device does not receive the erase instruction after being powered on; and after receiving the erase instruction, in response to the first identification value stored in the second register, determining the number of memory pages in the first memory block that have been subjected to program processing, and determining the number of program/erase cycles corresponding to the second memory blocks according to the number of memory pages that have been subjected to program processing.
7 . The method of claim 6 , further including: after receiving the erase instruction, in response to the first identification value stored in the second register, updating the first identification value stored in the second register to a second identification value.
8 . The method of claim 2 , further including: in response to the number of the received erase instructions reaching the number threshold, incrementing the number of program/erase cycles stored in the first register by 1.
9 . The method of claim 1 , further including: in response to the number of the received erase instructions reaching the number threshold, resetting the recorded number of the received erase instructions to 0.
10 . A memory device, comprising: a memory cell array including a plurality of memory blocks, wherein each memory block includes a plurality of memory pages; and a peripheral circuit coupled to the memory cell array and configured to: receive an erase instruction, and record a number of received erase instructions, wherein the erase instruction is to instruct the peripheral circuit to erase one memory block in the memory cell array; and in response to the number of the received erase instructions reaching a number threshold, select one memory page in a first memory block of the memory cell array to perform program processing, wherein the number threshold is equal to a total number of received erase instructions required for performing a preset number of program/erase cycles on each of second memory blocks in the memory cell array other than the first memory block, a number of memory pages in the first memory block that have been subjected to program processing is to indicate a number of program/erase cycles of the second memory blocks, and the preset number of program/erase cycles is equal to a ratio of a rated number of program/erase cycles corresponding to the second memory blocks to the number of memory pages in the first memory block.
11 . The memory device of claim 10 , wherein the peripheral circuit includes a plurality of registers and is further configured to: determine the number of memory pages in the first memory block that have been subjected to program processing, and determine the number of program/erase cycles corresponding to the second memory blocks according to the number of memory pages that have been subjected to program processing; and write the determined number of program/erase cycles to a first register in the plurality of registers.
12 . The memory device of claim 11 , wherein the peripheral circuit further includes an interface circuit and is further configured to: receive, by a query interface configured in the interface circuit, a query instruction for the number of program/erase cycles sent by a memory controller coupled with the memory device, and return the number of program/erase cycles stored in the first register to the memory controller.
13 . The memory device of claim 11 , wherein the peripheral circuit is configured to: determine a target address corresponding to a memory page that has been subjected to program processing most recently among the number of memory pages that have been subjected to program processing; and determine the number of program/erase cycles corresponding to the target address according to a correspondence relationship between addresses and the number of program/erase cycles.
14 . The memory device of claim 11 , wherein the peripheral circuit is configured to: after the memory device is powered on, determine the number of memory pages in the first memory block that have been subjected to program processing, and determine the number of program/erase cycles corresponding to the second memory blocks according to the number of memory pages that have been subjected to program processing.
15 . The memory device of claim 14 , wherein the peripheral circuit is configured to: after the memory device is powered on, write a first identification value to a second register in the plurality of registers, wherein the first identification value is to indicate that the memory device does not receive the erase instruction after being powered on; and after receiving the erase instruction, in response to the first identification value stored in the second register, determine the number of memory pages in the first memory block that have been subjected to program processing, and determine the number of program/erase cycles corresponding to the second memory blocks according to the number of memory pages that have been subjected to program processing.
16 . The memory device of claim 15 , wherein the peripheral circuit is further configured to: after receiving the erase instruction, in response to the first identification value stored in the second register, update the first identification value stored in the second register to a second identification value.
17 . The memory device of claim 11 , wherein the peripheral circuit is further configured to: in response to the number of the received erase instructions reaching the number threshold, increment the number of program/erase cycles stored in the first register by 1.
18 . A memory system, comprising: one or more memory devices each including: a memory cell array including a plurality of memory blocks, wherein each memory block includes a plurality of memory pages; and a peripheral circuit coupled to the memory cell array and configured to: receive an erase instruction, and record a number of received erase instructions, wherein the erase instruction is to instruct the peripheral circuit to erase one memory block in the memory cell array; and in response to the number of the received erase instructions reaching a number threshold, select one memory page in a first memory block of the memory cell array to perform program processing, wherein the number threshold is equal to a total number of received erase instructions required for performing a preset number of program/erase cycles on each of second memory blocks in the memory cell array other than the first memory block, a number of memory pages in the first memory block that have been subjected to program processing is to indicate a number of program/erase cycles of the second memory blocks, and the preset number of program/erase cycles is equal to a ratio of a rated number of program/erase cycles corresponding to the second memory blocks to the number of memory pages in the first memory block; and a memory controller coupled to the one or more memory devices and configured to control the one or more memory devices.
19 . The memory system of claim 18 , wherein the peripheral circuit includes a plurality of registers, and the peripheral circuit is configured to: determine the number of memory pages in the first memory block that have been subjected to program processing, and determining the number of program/erase cycles corresponding to the second memory blocks according to the number of memory pages that have been subjected to program processing; and write the determined number of program/erase cycles to a first register in the plurality of registers.
20 . The memory system of claim 19 , wherein the peripheral circuit further includes an interface circuit, and the peripheral circuit is configured to: receive, by a query interface configured in the interface circuit, a query instruction for the number of program/erase cycles sent by the memory controller, and return the number of program/erase cycles stored in the first register to the memory controller.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority to and the benefit of Chinese Patent Application 202410658907.0, filed on May 24, 2024, which is hereby incorporated by reference in its entirety. TECHNICAL FIELD The present application relates to the technical field of memory devices, and particularly to memory devices, control methods of memory devices, and memory systems. BACKGROUND A memory device comprises three basic operations of erase, write, and read. Generally, before data is written to a memory block in the memory device, data that has been stored in the memory block needs to be erased first, wherein the number of times the memory block is first erased and then written with data may be referred to as the number of program/erase cycles program/erase (PE) cycles. BRIEF DESCRIPTION OF THE DRAWINGS The drawings to be used in description of examples will be briefly introduced below in order to illustrate the technical solutions in the examples of the present application more clearly. Apparently, the drawings described below are only some examples of the present application. Those of ordinary skill in the art may obtain other drawings according to these drawings without inventive effort. FIG. 1 is a schematic diagram of an example system having a memory device provided by examples of the present application; FIG. 2 is a schematic diagram of an example memory card having a memory device provided by examples of the present application; FIG. 3 is a schematic diagram of an example solid-state drive having a memory device provided by examples of the present application; FIG. 4 is a schematic diagram of a memory device comprising a peripheral circuit provided by examples of the present application; FIG. 5 is a schematic diagram of an example memory cell array comprising a NAND memory string provided by examples of the present application; FIG. 6 is a schematic diagram of a memory device comprising a memory cell array and a peripheral circuit provided by examples of the present application; FIG. 7 is a schematic diagram of a memory device comprising a memory cell array and a peripheral circuit provided by examples of the present application; FIG. 8 is a flow diagram of a memory control method provided by examples of the present application; FIG. 9 is a schematic diagram of a method of determining a number of program/erase cycles provided by examples of the present application; FIG. 10 is a schematic diagram of a method of determining a number of program/erase cycles provided by examples of the present application; FIG. 11 is a flow diagram of a query method of a number of program/erase cycles of a memory block provided by examples of the present application; and FIG. 12 is a flow diagram of a method of recording a number of program/erase cycles provided by examples of the present application. DETAILED DESCRIPTION In order to clarity the objectives, technical solutions, and advantages of the present application, the implementations of the present application will be described in detail below with reference to the drawings. The number of program/erase cycles of the memory block is an important parameter for indicating a health degree of the memory device. As the number of the memory devices managed by a memory controller increases, the pressure of the memory controller to maintain the number of program/erase cycles is also increasing. FIG. 1 shows a block diagram of an example system 100 having a memory system according to some aspects of the present application. The system 100 may comprise a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a gaming console, a printer, a positioning apparatus, a wearable electronic apparatus, a smart sensor, a virtual reality (VR) apparatus, an augmented reality (AR) apparatus, or any other suitable electronic apparatus having a memory device. As shown in FIG. 1, the system 100 may comprise a host 108 and a memory system 102, and the memory system 102 is provided with one or more memory devices 104 and a memory controller 106. The host 108 may be a processor (e.g., a central processing unit (CPU)) or a system-on-chip (SoC) (e.g., application processor (AP)) of an electronic apparatus. The host 108 may be configured to send or receive data to or from the memory device 104. The memory device 104 may comprise any memory device disclosed in the present application. In an example, the memory device 104 comprises a NAND flash memory, such as a three-dimensional (3D) NAND flash memory. In some implementations, the memory controller 106 is coupled to the memory device 104 and the host 108, and is configured to control the memory device 104. The memory controller 106 may manage data stored in the memory device 104, and communicate with the host 108. In some implementations, the memory controller 106 is designed for operating in a low duty-cycle environment, such as secure digital (SD) cards, compact flash (CF) cards, univ