US-12626768-B2 - Memory device for effectively performing bit line precharge operation and operation method of the same

Abstract

A memory device, comprising: a memory cell array including a plurality of memory cell strings, and coupled between a plurality of bit lines and a plurality of word lines, the bit lines commonly coupled to a common source line, and a control portion suitable for: precharging the bit lines to a first level during a read operation for selected memory cells coupled to a selected word line of the word lines, and precharging the bit lines to a second level during a verify operation of a program operation for the selected memory cells, wherein the second level is lower than the first level by a set level.

Inventors

• Jae Yeop JUNG
• Dong Hun Kwak
• Se Chun Park

Assignees

• SK Hynix Inc.

Dates

Publication Date

20260512

Application Date

20231108

Priority Date

20230623

Claims (18)

1. 1 . A memory device, comprising: a memory cell array including a plurality of memory cell strings, and coupled between a plurality of bit lines and a plurality of word lines, the bit lines commonly coupled to a common source line; and a control portion suitable for: precharging the bit lines to a first level during a read operation for selected memory cells coupled to a selected word line of the word lines, and precharging the bit lines to a second level during a verify operation of a program operation for the selected memory cells, performing the program operation by repeating a program loop including a voltage application operation and the verify operation until the program operation is performed successfully, and wherein the second level is lower than the first level by a set level, and wherein the control portion adjusts the set level further according to a number of repetitions of the program loop.
2. 2 . The memory device of claim 1 , wherein the control portion is further suitable for adjusting the set level according to a physical position of the selected word line during the verify operation.
3. 3 . The memory device of claim 2 , wherein the control portion adjusts the set level by increasing the set level as the selected word line is positioned closer to the common source line.
4. 4 . The memory device of claim 2 , wherein the control portion adjusts the set level by increasing the set level in proportion to the number of repetitions.
5. 5 . The memory device of claim 2 , wherein the control portion is further suitable for increasing, in proportion to an increase in the set level, a level of a verification voltage applied to the selected word line during the verify operation.
6. 6 . The memory device of claim 1 , wherein the control portion includes a precharge control unit suitable for precharging the bit lines to one level among the first level and the second level.
7. 7 . The memory device of claim 6 , wherein the precharge control unit precharges the bit lines to: the first level during the read operation, and the second level during the verify operation.
8. 8 . The memory device of claim 7 , wherein the control portion further includes a positioning unit suitable for detecting a physical position of the selected word line, and wherein the precharge control unit is further suitable for adjusting the set level according to the physical position during the verify operation.
9. 9 . The memory device of claim 8 , wherein the precharge control unit adjusts the set level by increasing the set level as the selected word line is positioned closer to the common source line.
10. 10 . The memory device of claim 8 , wherein the control portion further includes a program operating unit suitable for performing the program operation by repeating the program loop including the voltage application operation and the verify operation until the program operation is performed successfully, and wherein the precharge control unit adjusts the set level further according to a number of repetitions of the program loop.
11. 11 . The memory device of claim 10 , wherein the precharge control unit adjusts the set level by increasing the set level in proportion to the number of repetitions.
12. 12 . The memory device of claim 10 , wherein the program operating unit is further suitable for increasing, in proportion to an increase in the set level, a level of a verification voltage applied to the selected word line during the verify operation.
13. 13 . A method for operating a memory device including a memory cell array having a plurality of memory cell strings, and coupled between a plurality of bit lines and a plurality of word lines, the method comprising: precharging the bit lines to a first level during a read operation for selected memory cells included in cell strings coupled to a selected word line of the word lines; and precharging the bit lines to a second level during a verify operation of a program operation for the selected memory cells, performing the program operation by repeating a program loop including a voltage application operation and the verify operation until the program operation is performed successfully, and wherein the second level is lower than the first level by a set level, and wherein the set level is adjusted further according to a number of repetitions of the program loop.
14. 14 . The method of claim 13 , further comprising adjusting the set level according to a physical position of the selected word line during the verify operation.
15. 15 . The method of claim 14 , wherein the adjusting includes increasing the set level as the selected word line is positioned closer to the common source line.
16. 16 . The method of claim 14 , wherein the adjusting includes increasing the set level in proportion to the number of repetitions.
17. 17 . The method of claim 14 , further comprising increasing, in proportion to an increase in the set level, a level of a verification voltage applied to the selected word line during the verify operation.
18. 18 . An operating method of a memory device, the operating method comprising: lowering, during a verify operation in a program operation on a row of memory cells, a precharge level of bit lines by an amount from the precharge level for a read operation on the row; increasing the amount as the row is disposed closer to a common source line and as a number of program loops increases during the program operation; and increasing, in proportion to the amount, a level of a verification voltage applied to the row.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS The present application claims priority of Korean Patent Application No. 10-2023-0081017, filed on Jun. 23, 2023, which is incorporated herein by reference in its entirety. BACKGROUND 1. Field Various embodiments of the present invention relate to a semiconductor memory device, and more particularly, to a memory device for effectively performing a bit line precharge operation, and a method for operating the memory device. 2. Description of the Related Art Memory systems are storage devices embodied using a semiconductor such as silicon (Si), germanium (Ge), gallium arsenide (GaAs), indium phosphide (InP), or the like. The memory systems are classified into a volatile memory device and a nonvolatile memory device. The volatile memory device is a memory device in which data stored therein is lost when power supply is interrupted. Representative examples of the volatile memory device include static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), etc. The nonvolatile memory device is a memory device in which data stored therein is retained even when power supply is interrupted. Representative examples of the nonvolatile memory device include a read only memory (ROM), a programmable ROM (PROM), an electrically programmable ROM (EPROM), an electrically erasable programmable ROM (EEPROM), a flash memory, a phase-change random access memory (PRAM), a magnetic RAM (MRAM), a resistive RAM (RRAM), a ferroelectric RAM (FRAM), etc. Flash memories are chiefly classified into a NOR-type memory and NAND-type memory. A program operation for the multiple memory cells that are included in a nonvolatile memory device may be performed by repeating a program loop including a voltage application operation and a verify operation. Here, the voltage application operation may be an operation of changing the threshold voltages of memory cells selected as a program target, while applying a program pulse, having a voltage increased step by step, to a word line to which the memory cells selected as the program target have been connected. Furthermore, the verify operation may be an operation of checking whether threshold voltage levels of the memory cells selected as the program target have reached a target voltage level. Furthermore, a read operation for the multiple memory cells that are included in a nonvolatile memory device may be an operation of sensing whether threshold voltage levels of the memory cells selected as the read target have reached a read voltage level. SUMMARY Embodiments of the present invention are directed to a memory device capable of varying a bit line precharge level according to whether a requested operation is a verify operation or a read operation included in a program operation, and a method for operating the memory device. The technical problems desired to be achieved by the embodiments of the present invention are not limited to the technical problems mentioned above, and other technical problems not mentioned above may also be clearly understood by those of ordinary skill in the art to which the present invention pertains from the description below. In accordance with an embodiment of the present invention, a memory device may include: a memory cell array including a plurality of memory cell strings, and coupled between a plurality of bit lines and a plurality of word lines, the bit lines commonly coupled to a common source line; and a control portion suitable for: precharging the bit lines to a first level during a read operation for selected memory cells coupled to a selected word line of the word lines, and precharging the bit lines to a second level during a verify operation of a program operation for the selected memory cells, wherein the second level is lower than the first level by a set level. In accordance with another embodiment of the present invention, a method for operating a memory device including a memory cell array having a plurality of memory cell strings, and coupled between a plurality of bit lines and a plurality of word lines, the method may include: precharging the bit lines to a first level during a read operation for selected memory cells included in cell strings coupled to a selected word line of the word lines; and precharging the bit lines to a second level during a verify operation of a program operation for the selected memory cells, wherein the second level is lower than the first level by a set level. In accordance with another embodiment of the present invention, an operating method of a memory device, the operating method may include: lowering, during a verify operation in a program operation on a row of memory cells, a precharge level of bit lines by an amount from the precharge level for a read operation on the row; increasing the amount as the row is disposed closer to a common source line and/or as a number of program loops increases during the program operation; and increasing, in proportion to the amount, a level of