US-12626770-B2 - Control gate voltage generating circuit for non-volatile memory

US12626770B2US 12626770 B2US12626770 B2US 12626770B2US-12626770-B2

Abstract

A control gate voltage generating circuit for a non-volatile memory is provided. After the non-volatile memory leaves the factory, the control gate voltage is appropriately adjusted by the control gate voltage generating circuit according to the characteristics changes of the memory cells. When the read action is performed, the control gate voltage generating circuit provides the adjusted control gate voltage to the control gate line of the array structure. The magnitude of the reference current can be maintained in the range between the read current in the erase state and the read current in the program state. Consequently, the storage state of the selected memory cell can be accurately determined, and the life time of the non-volatile memory will be extended.

Inventors

Yu-Hsuan Cheng

Assignees

EMEMORY TECHNOLOGY INC.

Dates

Publication Date: 20260512
Application Date: 20240806

Claims (13)

1 . A control gate voltage generating circuit for a non-volatile memory, the non-volatile memory comprising an array structure, the array structure being connected with a source line and a control gate line, the control gate voltage generating circuit being connected with the control gate line, the control gate voltage generating circuit comprising: 2N reference memory cells, wherein first terminals of the 2N reference memory cells are connected with the source line, control gate terminals of the 2N reference memory cells are connected with the control gate line, select gate terminals of the 2N reference memory cells are connected with a reference word line, and second terminals of the 2N reference memory cells are respectively connected with 2N reference bit lines, wherein N is a positive integer; a switching circuit connected with the 2N reference bit lines, wherein when a read action is performed, a first read voltage is provided to the source line, an on voltage is provided to the reference word line, the 2N reference bit lines are connected with a first node through the switching circuit, and the 2N reference memory cells generate a total current flowed to the first node, wherein the total current is a sum of plural read currents generated by a first number of the reference memory cells in a program state and the read currents generated by a second number of the reference memory cells in an erase state, wherein the sum of the first number and the second number is equal to 2N; a current mirror, wherein a current input terminal of the current mirror receives a reference current, and a current mirroring terminal of the current mirror is connected with the first node to receive the total current, wherein a ratio of the reference current to the total current is 1/(2N); and a voltage tracking circuit comprising a first input terminal, a second input terminal and an output terminal, wherein the first input terminal of the voltage tracking circuit receives a second read voltage, the second input terminal of the voltage tracking circuit is connected with the first node, and the output terminal of the voltage tracking circuit generates a first control gate voltage, and the first control gate voltage is transmitted to the control gate line.
2 . The control gate voltage generating circuit as claimed in claim 1 further comprises: a selecting circuit, wherein a first input terminal of the selecting circuit is connected with the output terminal of the voltage tracking circuit, and an output terminal of the selecting circuit is connected with the control gate line, wherein when the read action is performed, the first terminal of the selecting circuit is connected with the output terminal of the selecting circuit, so that the first control gate voltage is transmitted to the control gate line for the read action.
3 . The control gate voltage generating circuit as claimed in claim 2 , wherein the selecting circuit further comprises: a second input terminal receiving a second control gate voltage; and a third input terminal receiving a third control gate voltage, wherein when a program action is performed, the second terminal of the selecting circuit is connected with the output terminal of the selecting circuit, so that the control gate line outputs the second control gate voltage for the program action, wherein when an erase action is performed, the third terminal of the selecting circuit is connected with the output terminal of the selecting circuit, so that the control gate line outputs the third control gate voltage for the erase action.
4 . The control gate voltage generating circuit as claimed in claim 1 , wherein a first reference memory cell of the 2N reference memory cells comprises: a memory transistor, wherein a first drain/source terminal of the memory transistor is the first terminal of the first reference memory cell, and a control gate of the memory transistor is the control gate terminal of the first reference memory cell; and a select transistor, wherein a first drain/source terminal of the select transistor is connected with a second drain/source terminal of the memory transistor, a second drain/source terminal of the select transistor is the second terminal of the first reference memory cell, and a select gate of the select transistor is the select gate terminal of the first reference memory cell.
5 . The control gate voltage generating circuit as claimed in claim 4 , wherein the memory transistor is a charge-trap transistor or a floating gate transistor.
6 . The control gate voltage generating circuit as claimed in claim 1 , wherein in the 2N reference memory cells, N reference memory cells are in the program state, and the other N memory cells are in the erase state, wherein the total current is a sum of the read currents generated by the N reference memory cells in the program state and the read currents generated by the N memory cells in the erase state.
7 . The control gate voltage generating circuit as claimed in claim 6 , wherein when an erase action is performed on plural memory cells in the array structure, the erase action is also performed on the 2N reference memory cells, wherein after the erase action is completed, the N reference memory cells of the 2N reference memory cells are subjected to a program action and programmed to the program state, and the other N reference memory cells of the 2N reference memory cells are maintained in the erase state.
8 . The control gate voltage generating circuit as claimed in claim 1 , wherein the current mirror comprises: a first transistor, wherein a first drain/source terminal of the first transistor is the current input terminal of the current mirror, a second drain/source terminal of the first transistor is connected with a ground terminal, and a gate terminal of the first transistor is connected with the first drain/source terminal of the first transistor; and a second transistor, wherein a first drain/source terminal of the second transistor is the current mirroring terminal of the current mirror, a second drain/source terminal of the second transistor is connected with the ground terminal, and a gate terminal of the second transistor is connected with the gate terminal of the first transistor, wherein a ratio of a size of the first transistor to a size of the transistor is 1:2N.
9 . The control gate voltage generating circuit as claimed in claim 1 , wherein the voltage tracking circuit comprises an operational amplifier, wherein a negative input terminal of the operational amplifier receives the second read voltage, a positive input terminal of the operational amplifier is connected with the first node, and an output terminal of the operational amplifier generates the first control gate voltage.
10 . The control gate voltage generating circuit as claimed in claim 1 , wherein the voltage tracking circuit comprises: a comparator, wherein a negative input terminal of the comparator receives the second read voltage, a positive input terminal of the comparator is connected with the first node, and an output terminal of the comparator generates a comparison output signal; a controller receiving the comparison output signal and generating a control signal; and a multiplexer with plural input terminals, wherein the plural input terminals of the multiplexer respectively receive plural input voltages, wherein according to the control signal, one of the plural input voltages is transmitted to an output terminal of the multiplexer and served as the control gate voltage.
11 . The control gate voltage generating circuit as claimed in claim 1 , wherein the control gate voltage generating circuit further comprises a sensing circuit for receiving the reference current, and the sensing circuit is connected with the switching circuit, wherein when a program action or an erase action is performed, the 2N reference bit lines are connected with the sensing circuit through the switching circuit.
12 . The control gate voltage generating circuit as claimed in claim 11 , wherein the switching circuit comprises 2N switches, wherein first terminals of the 2N switches are respectively connected with the corresponding 2N reference bit lines, second terminals of the 2N switches are connected with the first node, and third terminals of the 2N switches are connected with the sensing circuit, wherein when the read action is performed, the first terminal and the second of each of the 2N switches are connected with each other, wherein when a program action or an erase action is performed, the first terminal and the third terminal of each of the 2N switches are connected with each other.
13 . The control gate voltage generating circuit as claimed in claim 12 , wherein a first switch of the 2N switches comprises: a first transistor, wherein a first drain/source terminal of the first transistor is connected with a first reference bit line of the N reference bit lines, a second drain/source terminal of the first transistor is connected with the first node, and a gate terminal of the first transistor receives a first sub-control signal; and a second transistor, wherein a first drain/source terminal of the second transistor is connected with the first reference bit line, a second drain/source terminal of the second transistor is connected with the sensing circuit, and a gate terminal of the second transistor receives a second sub-control signal, wherein when the read action is performed, the first sub-control signal is activated, the second sub-control signal is not activated, so that the first reference bit line is connected with the first node; wherein when the program action or the erase action is performed, the first sub-control signal is not activated, and the second sub-control signal is activated, so that the first reference bit line is connected with the sensing circuit.

Description

This application claims the benefit of U.S. provisional application Ser. No. 63/532,701, filed Aug. 15, 2023, the subject matter of which is incorporated herein by references. FIELD OF THE INVENTION The present invention relates to an internal circuit of a non-volatile memory, and more particularly to a control gate voltage generating circuit for a non-volatile memory. BACKGROUND OF THE INVENTION As known, non-volatile memories have been widely used in a variety of electronic products such as SD cards or solid state drives (SSDs). Generally, a non-volatile memory comprises a memory array. The memory array comprises plural non-volatile memory cells. Each memory cell comprises a memory transistor. For example, the memory transistor is a charge-trap transistor or a floating gate transistor. Hereinafter, the structure of a memory cell will be described. FIG. 1A is a schematic cross-sectional view illustrating a memory cell. FIG. 1B is an equivalent circuit of the memory cell shown in FIG. 1B. The memory cell 100 comprises a select transistor MS and a memory transistor MM. For example, the select transistor MS and the memory transistor MM are p-type transistors. As shown in FIG. 1A, three p-doped regions 51, 53 and 55 are formed under the surface of an N-well region NW. A gate structure 10 is located over the surface of the N-well region NW between the p-doped region 53 and the p-doped region 55. A gate structure 20 is located over the surface of the N-well region NW between the p-doped region 51 and the p-doped region 53. The gate structure 10 comprises a gate dielectric layer 11 and a select gate layer 13. The gate structure 20 comprises a charge storage structure 26 and a control gate layer 27. The charge storage structure 26 comprises a gate dielectric layer 21, a charge storage layer 23 and an isolation layer 25. The N-well region NW, the gate structure 10, the p-doped region 53 and the p-doped region 55 are collaboratively formed as the select transistor MS. The N-well region NW, the gate structure 20, the p-doped region 51 and the p-doped region 53 are collaboratively formed as the memory transistor MM. The select gate layer 13 and the control gate layer 27 are polysilicon layers. In addition, the gate dielectric layers 11 and 21 and the isolation layer 25 are oxide layers, and the charge storage layer 23 is a nitride layer or a polysilicon layer. In other words, the charge storage structure 26 is an oxide-nitride-oxide (ONO) structure or an oxide-polysilicon-oxide structure. In case that the charge storage structure 26 is the oxide-nitride-oxide (ONO) structure, the memory transistor MM is a charge-trap transistor. In case that the charge storage structure 26 is the oxide-polysilicon-oxide structure, the memory transistor MM is a floating gate transistor. The memory cell 100 is a four-terminal device. A first terminal T1 of the memory cell 100 is electrically connected with the p-doped region 51. A second terminal T2 of the memory cell 100 is electrically connected with the p-doped region 55. A control gate terminal TCG of the memory cell 100 is electrically connected with the control gate layer 27. A select gate terminal TSG of the memory cell 100 is electrically connected with the select gate layer 13. As shown in FIG. 1B, the memory transistor MM comprises a charge storage layer 23. The first drain/source terminal of the memory transistor MM is connected with the first terminal T1 of the memory cell 100. The second drain/source terminal of the memory transistor MM is connected with the first drain/source terminal of the select transistor MS. The second drain/source terminal of the select transistor MS is connected with the second terminal T2 of the memory cell 100. The select gate of the select transistor MS is connected with the select gate terminal TSG of the memory cell 100. The control gate of the memory transistor MM is connected with the control gate terminal TCG of the memory cell 100. By providing proper bias voltages to the four terminals of the memory cell 100, a program action or an erase action can be performed on the memory cell 100. For example, in case that no carriers are stored in the charge storage layer 23 of the memory transistor MM, the memory cell 100 is in an erase state. When the program action is performed on the memory cell 100, the carriers are injected into the charge storage layer 23 of the memory transistor MM. Consequently, the carriers are stored in the charge storage layer 23 of the memory transistor MM, and the memory cell 100 is in a program state. When the erase action is performed on the memory cell 100, the carriers are ejected from the charge storage layer 23 of the memory transistor MM. Consequently, the memory cell 100 is in the erase state. For example, the carriers are electrons or holes. FIG. 2A schematically illustrates the bias voltages for performing a read action on the memory cell shown in FIG. 1A, in which the memory cell is in the program state. FIG.