US-12626773-B2 - Memory device and memory system including plural switch transistors in a string

Abstract

A memory device includes a cell array and control circuitry. The cell array includes plural memory cells and plural switch transistors. The control circuitry is configured to perform checking and recovery operations regarding operating states of the plural switch transistors during operation margins set for the plural data input/output operations.

Inventors

• Dong Hun Kwak

Assignees

• SK Hynix Inc.

Dates

Publication Date

20260512

Application Date

20231103

Priority Date

20230630

Claims (19)

1. 1 . A memory device comprising: a cell array comprising plural memory cells and plural switch transistors; and control circuitry configured to perform at least one of a checking operation and a recovery operation regarding the plural switch transistors during operation margins set for plural data input/output operations performed in the cell array, wherein the checking operation checks threshold voltages of the plural switch transistors to determine whether the plural switch transistors are deteriorated and the recovery operation shifts a threshold voltage of a deteriorated switch transistor among the plural switch transistors, wherein the control circuitry is configured to perform the checking operation during operation margins based on a programmed data value of plural program operations.
2. 2 . The memory device according to claim 1 , wherein the plural switch transistors comprise: at least one drain select transistor configured to control connection between the plural memory cells and a bit line; at least one source select transistor configured to control connection between the plural memory cells and a common source line; and at least one central switching transistor disposed between the plural memory cells.
3. 3 . The memory device according to claim 2 , wherein the at least one central switching transistor is disposed between two vertically stacked portions each comprising at least some of the plural memory cells.
4. 4 . The memory device according to claim 1 , wherein the plural data input/output operations comprise: one or more erase operations for erasing data remained in the plural memory cells; and one or more program operations for programming data in the plural memory cells.
5. 5 . The memory device according to claim 4 , wherein the control circuitry is configured to perform the checking operation during an operation margin set for the one or more erase operations and the recovery operation during an operation margin set for the one or more program operations.
6. 6 . The memory device according to claim 1 , wherein the control circuitry is configured to divide the at least one of the checking operation and the recovery operation into plural unit operations based on locations of the plural switch transistors.
7. 7 . The memory device according to claim 6 , wherein the control circuitry is configured to perform the unit operations for each of the plural switch transistors during the operation margin set for each of the plural data input/output operations.
8. 8 . The memory device according to claim 6 , wherein the control circuitry is configured to perform the unit operations on a single switch transistor during the operation margins set for the plural data input/output operations.
9. 9 . The memory device according to claim 1 , further comprising a buffer configured to store location information of deteriorated switch transistors among the plural switch transistors.
10. 10 . The memory device according to claim 9 , wherein the control circuitry is configured to generate a switch transistor recovery command comprising the location information, based on which one of the plural data input/output operations is performed in the cell array.
11. 11 . The memory device according to claim 1 , wherein the control circuitry is configured to generate a control signal for the checking operation when an erase command is input.
12. 12 . The memory device according to claim 1 , wherein the control circuitry is configured to generate a control signal for the recovery operation when a program command is input.
13. 13 . A memory system comprising: a memory device comprising plural memory cells and plural switch transistors; and a controller configured to generate a program command for a program operation on the plural memory cells based on whether to perform a checking or a recovery operation regarding the plural switch transistors, wherein the checking operation checks threshold voltages of the plural switch transistors to determine whether the plural switch transistors are deteriorated and the recovery operation shifts a threshold voltage of a deteriorated switch transistor among the plural switch transistors, wherein the controller is further configured to perform the checking operation during operation margins based on a programmed data value of plural program operations.
14. 14 . The memory system according to claim 13 , wherein the program command is one of: a first program command for performing the program operation along with the checking and recovery operations; and a second program command for performing the program operation only without the checking and recovery operations.
15. 15 . The memory system according to claim 14 , wherein the controller is configured to generate the first program command based on program data which is to be programmed as a part of multi-bit data in the plural memory cells of the cell array during the program operation.
16. 16 . The memory system according to claim 13 , wherein the controller is configured to: generate an erase command for an erase operation for erasing data remained in the plural memory cells and the checking operation for checking the threshold voltages of the plural switch transistors; and generate the program command for the program operation and the recovery operation for shifting threshold voltages of the deteriorated switch transistor among the plural switch transistors, wherein the controller is further configured to perform the checking operation during operation margins based on a programmed data value of plural program operations.
17. 17 . The memory system according to claim 13 , wherein the plural switch transistors comprise: at least one drain select transistor configured to control connection between the plural memory cells and a bit line; at least one source select transistor configured to control connection between the plural memory cells and a common source line; and at least one central switching transistor disposed between the plural memory cells.
18. 18 . A memory system comprising: a memory device comprising plural memory cells and plural switch transistors; and a controller configured to transmit plural data input/output commands to the memory device, the plural data input/output commands designed for the memory device to perform at least one of a checking operation and a recovery operation regarding the plural switch transistors during plural data input/output operations performed based on the plural data input/output commands, wherein the checking operation checks threshold voltages of the plural switch transistors to determine whether the plural switch transistors are deteriorated and the recovery operation shifts a threshold voltage of a deteriorated switch transistor among the plural switch transistors.
19. 19 . The memory system according to claim 18 , wherein the plural data input/output commands comprise a program command for the memory device to perform a program operation for programming data therein with performing the at least one of the checking operation and the recovery operation.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This patent application claims the benefit of priority under 35 U.S.C. § 119(a) to Korean Patent Application No. 10-2023-0085219, filed on Jun. 30, 2023, the entire disclosure of which is incorporated herein by reference. TECHNICAL FIELD One or more embodiments of the present disclosure described herein relate to a memory device, and more particularly, to plural switch transistors coupled to plural memory cells included in the memory device. BACKGROUND A data processing system including a memory system or a data storage device can store more amounts of data in the data storage device and store data in the data storage device more quickly. The memory system has been developed to output data stored in the data storage device more quickly. The data storage device may include non-volatile memory cells and/or volatile memory cells for storing data. BRIEF DESCRIPTION OF THE DRAWINGS The description herein makes reference to the accompanying drawings wherein like reference numerals refer to like parts throughout the figures. FIG. 1 illustrates a memory device according to an embodiment of the present disclosure. FIG. 2 illustrates a memory device according to another embodiment of the present disclosure. FIG. 3 illustrates a memory cell array according to another embodiment of the present disclosure. FIG. 4 illustrates check and recovery operations regarding operating states of switch transistors according to another embodiment of the present disclosure. FIG. 5 illustrates the check and recovery operations regarding the operating states of switch transistors during an erase operation according to an embodiment of the present disclosure. FIG. 6 illustrates the check and recovery operations regarding the operating states of switch transistors during data input/output operations according to an embodiment of the present disclosure. FIG. 7 illustrates a finite state machine included in a memory device according to another embodiment of the present disclosure. FIG. 8 illustrates the check and recovery operations regarding the operating states of switch transistors during a program operation according to an embodiment of the present disclosure. FIG. 9 illustrates a memory system according to another embodiment of the present disclosure. FIG. 10 illustrates a memory system according to another embodiment of the present disclosure. FIG. 11 illustrates a first example of the check and recovery operations regarding the operating states of switch transistors during data input/output operations according to an embodiment of the present disclosure. FIG. 12 illustrates a second example of the check and recovery operations regarding the operating states of switch transistors during data input/output operations according to an embodiment of the present disclosure. DETAILED DESCRIPTION Various embodiments of the present disclosure are described below with reference to the accompanying drawings. Elements and features of this disclosure, however, may be configured or arranged differently to form other embodiments, which may be variations of any of the disclosed embodiments. In this disclosure, references to various features (e.g., elements, structures, modules, components, steps, operations, characteristics, etc.) included in “one embodiment,” “example embodiment,” “an embodiment,” “another embodiment,” “some embodiments,” “various embodiments,” “other embodiments,” “alternative embodiment,” and the like are intended to mean that any such features are included in one or more embodiments of the present disclosure, but may or may not necessarily be combined in the same embodiments. In this disclosure, the terms “comprise,” “comprising,” “include,” and “including” are open-ended. As used in the appended claims, these terms specify the presence of the stated elements and do not preclude the presence or addition of one or more other elements. The terms in a claim do not foreclose the apparatus from including additional components e.g., an interface unit, circuitry, etc. In this disclosure, various units, circuits, or other components may be described or claimed as “configured to” perform a task or tasks. In such contexts, “configured to” is used to connote structure by indicating that the blocks/units/circuits/components include structure (e.g., circuitry) that performs one or more tasks during operation. As such, the block/unit/circuit/component can be said to be configured to perform the task even when the specified block/unit/circuit/component is not currently operational, e.g., is not turned on nor activated. Examples of block/unit/circuit/component used with the “configured to” language include hardware, circuits, memory storing program instructions executable to implement the operation, etc. Additionally, “configured to” can include a generic structure, e.g., generic circuitry, that is manipulated by software and/or firmware, e.g., an FPGA or a general-purpose processor executing software to