US-12626775-B2 - Magnetic memory and memory system

US12626775B2US 12626775 B2US12626775 B2US 12626775B2US-12626775-B2

Abstract

A first circuit outputs first information indicating presence/absence of a magnetic wall between two adjacent portions among portions of a magnetic body, and outputs second information based on the combination of magnetization states of the two portions. A first storage circuit stores first bits corresponding to the portions, respectively. A most significant bit of the first bits has a value independent of a magnetization state of its corresponding one of the portions, and the first bits have a value based on the first information. A second storage circuit stores the second information. A second circuit causes the first storage circuit to output the first bits when a value of a least significant bit of the first bits matches a value of the second information, and otherwise to output third bits having inverse values of the first bits.

Inventors

Shogo Muto
Masanobu Shirakawa
Hideki Yamada
Ryo Yamaki
Yoshihiro Ueda
Tsuyoshi Kondo

Assignees

KIOXIA CORPORATION

Dates

Publication Date: 20260512
Application Date: 20240705
Priority Date: 20230710

Claims (20)

1 . A magnetic memory comprising: a magnetic body extending in a first direction and including portions aligned in the first direction; a first circuit configured to output first information indicating presence or absence of a magnetic wall between two portions which are adjacent among the portions, and second information based on a combination of magnetization states of the two portions; a first storage circuit configured to store first bits respectively corresponding to the portions, where a most significant bit of the first bits has a value independent of a magnetization state of its corresponding portion among the portions, and each of the first bits has a value based on the first information; a second storage circuit configured to store the second information in a second bit; and a second circuit configured to cause the first storage circuit to output the first bits when a value of a least significant bit of the first bits matches a value of the second information stored in the second storage circuit, and cause the first storage circuit to output third bits having inverse values of the first bits in respective bits when the value of the least significant bit of the first bits is different from the value of the second information stored in the second storage circuit.
2 . The memory according to claim 1 , wherein each of the first bits has the same value as an adjacent bit aligned on a side of the most significant bit of the first bits when it is determined that a corresponding single portion among the portions and an adjacent portion aligned with the corresponding single portion in the first direction have the same magnetization state, and has a value different from the adjacent bit when it is determined that the corresponding single portion and the adjacent portion have different magnetization states.
3 . The memory according to claim 2 , wherein every time the first information is received, the first storage circuit shifts a value of each of the first bits to an adjacent bit, and stores a value based on the received first information in the least significant bit of the first bits.
4 . The memory according to claim 1 , wherein the second information has a first value when a first portion among the portions has a first magnetization state and the first portion, before a magnetic wall in the portions shifts in the first direction, has a second magnetization state, and has a second value when the first portion has the second magnetization state and the first portion, before the shift of the magnetic wall, has the first magnetization state.
5 . The memory according to claim 4 , wherein the first magnetization state is a state of magnetization toward a second direction, the second magnetization state is a state of magnetization toward a third direction, and the third direction is different from the second direction.
6 . The memory according to claim 1 , wherein every time a magnetic wall in the portions shifts in the first direction, the first circuit outputs the first information and outputs the second information based on a magnetization state of a first portion among the portions and a magnetization state of the first portion before the shift of the magnetic wall.
7 . The memory according to claim 1 , wherein every time the second information is received, the second storage circuit updates the value of the second bit with the received second information.
8 . The memory according to claim 1 , further comprising: a third storage circuit configured to store fourth bits, wherein every time the first information is received, the third storage circuit shifts a value of each of the fourth bits to an adjacent bit, and stores a value based on the received first information in a least significant bit of the fourth bits, the first information has a third value when it is determined that a magnetic wall exists, the second storage circuit stores fifth bits, every time the second information is received, the second storage circuit shifts a value of each of the fifth bits to an adjacent bit, and stores a value based on the received second information in a least significant bit of the fifth bits, and the second bit is the bit in the same place as a least significant bit of the fourth bits, and has the third value.
9 . A memory system comprising: a memory controller; a magnetic memory; a magnetic body extending in a first direction and including portions aligned in the first direction; a first circuit configured to output first information indicating presence or absence of a magnetic wall between two portions which are adjacent among the portions, and second information based on a combination of magnetization states of the two portions; a first storage circuit configured to store first bits respectively corresponding to the portions, where a most significant bit of the first bits has a value independent of a magnetization state of its corresponding portion among the portions, and each of the first bits has a value based on the first information; a second storage circuit configured to store the second information in a second bit; and a second circuit configured to cause the first storage circuit to output the first bits when a value of a least significant bit of the first bits matches a value of the second information stored in the second storage circuit, and cause the first storage circuit to output third bits having inverse values of the first bits in respective bits when the value of the least significant bit of the first bits is different from the value of the second information stored in the second storage circuit.
10 . The system according to claim 9 , wherein each of the first bits has the same value as an adjacent bit aligned on a side of the most significant bit of the first bits when it is determined that a corresponding single portion among the portions and an adjacent portion aligned with the corresponding single portion in the first direction have the same magnetization state, and has a value different from the adjacent bit when it is determined that the corresponding single portion and the adjacent portion have different magnetization states.
11 . The system according to claim 10 , wherein every time the first information is received, the first storage circuit shifts a value of each of the first bits to an adjacent bit, and stores a value based on the received first information in the least significant bit of the first bits.
12 . The system according to claim 9 , wherein the second information has a first value when a first portion among the portions has a first magnetization state and the first portion, before a magnetic wall in the portions shifts in the first direction, has a second magnetization state, and has a second value when the first portion has the second magnetization state and the first portion, before the shift of the magnetic wall, has the first magnetization state.
13 . The system according to claim 12 , wherein the first magnetization state is a state of magnetization toward a second direction, the second magnetization state is a state of magnetization toward a third direction, and the third direction is different from the second direction.
14 . The system according to claim 9 , wherein every time a magnetic wall in the portions shifts in the first direction, the first circuit outputs the first information and outputs the second information based on a magnetization state of a first portion among the portions and a magnetization state of the first portion before the shift of the magnetic wall.
15 . The system according to claim 9 , wherein every time the second information is received, the second storage circuit updates the value of the second bit with the received second information.
16 . The system according to claim 9 , further comprising: a third storage circuit configured to store fourth bits, wherein every time the first information is received, the third storage circuit shifts a value of each of the fourth bits to an adjacent bit, and stores a value based on the received first information in a least significant bit of the fourth bits, the first information has a third value when it is determined that a magnetic wall exists, the second storage circuit stores fifth bits, every time the second information is received, the second storage circuit shifts a value of each of the fifth bits to an adjacent bit, and stores a value based on the received second information in a least significant bit of the fifth bits, and the second bit is the least significant bit of the fourth bits, and has the third value.
17 . The system according to claim 16 , wherein the magnetic memory comprises the magnetic body, the first circuit, the first storage circuit, and the second storage circuit, the memory controller comprises the second circuit, and the memory controller receives read data including one of the first bits and the third bits, and causes the magnetic memory to output the fourth bits and the fifth bits when error correction on the read data fails.
18 . The system according to claim 16 , wherein the magnetic memory comprises the magnetic body, the first circuit, the first storage circuit, and the second storage circuit, the memory controller transmits a first command to the magnetic memory, and when the first command is received, the magnetic memory outputs the first bits, the fourth bits, and the fifth bits.
19 . The system according to claim 9 , wherein the magnetic memory comprises the magnetic body, the first circuit, the first storage circuit, the second storage circuit, and the second circuit.
20 . The system according to claim 9 , wherein the magnetic memory comprises the magnetic body, the first circuit, the first storage circuit, and the second storage circuit, and the memory controller comprises the second circuit.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2023-112947, filed Jul. 10, 2023, the entire contents of which are incorporated herein by reference. FIELD Embodiments described herein relate generally to a magnetic memory and a memory system. BACKGROUND There is known a memory system including a memory and a memory controller. Examples of the memory include a magnetic memory using a magnetic body. The memory system is demanded to be capable of accurate data storing and output. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an example of functional blocks of an information processing system including a memory system according to the first embodiment. FIG. 2 is a block diagram showing an example of functional blocks of the memory system according to the first embodiment. FIG. 3 is a block diagram showing an example of functional blocks of a magnetic memory of the memory system according to the first embodiment. FIG. 4 is a view showing an example of components of a memory cell array of the memory system according to the first embodiment. FIG. 5 is a view showing an example of a partial structure of the memory cell array of the memory system according to the first embodiment. FIG. 6 is a view showing an example of the structure of a magnetic body and a layer stack of the memory system according to the first embodiment. FIG. 7 is a block diagram showing an example of components of a read circuit of the memory system according to the first embodiment. FIG. 8 is a flowchart showing the procedure of data writing by the magnetic memory of the memory system according to the first embodiment. FIG. 9 is a view showing a state concerning some elements during an operation in the memory system according to the first embodiment. FIGS. 10, 11, 12, 13, and 14 are views showing states concerning some components during the operation in the memory system according to the first embodiment. FIG. 15 is a flowchart showing the procedure of data reading by the magnetic memory of the memory system according to the first embodiment. FIG. 16 is a flowchart showing the procedure of data reading by the memory system according to the first embodiment. FIG. 17 is a view showing unintended switching of the magnetization state of unit portion. FIG. 18 is a block diagram showing an example of functional blocks of a memory controller of a memory system according to the second embodiment. FIG. 19 is a flowchart showing the procedure of data reading by a magnetic memory of the memory system according to the second embodiment. FIG. 20 is a flowchart showing the procedure of data reading by the memory system according to the second embodiment. FIG. 21 is a block diagram showing an example of functional blocks of the magnetic memory of a memory system according to the third embodiment. FIG. 22 is a view showing states concerning some elements during an operation in the memory system according to the third embodiment. FIG. 23 is a flowchart showing the procedure of data reading by a magnetic memory of the memory system according to the third embodiment. FIG. 24 is a flowchart showing the procedure of data reading by the magnetic memory of the memory system according to the third embodiment. FIGS. 25 and 26 are flowcharts showing the procedure of data reading by the memory system according to the third embodiment. FIG. 27 is a view showing an example of data generated during an operation in the memory system according to the third embodiment. FIG. 28 is a flowchart showing the procedure of data reading by the magnetic memory of a memory system according to the fourth embodiment. FIG. 29 is a flowchart showing the procedure of data reading by the memory system according to the fourth embodiment. DETAILED DESCRIPTION In one embodiment, a magnetic memory includes a magnetic body; a first circuit; a first storage circuit; a second storage circuit; and a second circuit. The magnetic body extends in a first direction and includes portions aligned in the first direction. The first circuit is configured to output first information indicating presence or absence of a magnetic wall between two portions which are adjacent among the portions, and second information based on the combination of magnetization states of the two portions. The first storage circuit is configured to store first bits respectively corresponding to the portions, where a most significant bit of the first bits has a value independent of a magnetization state of its corresponding portion among the portions, and each of the first bits has a value based on the first information. The second storage circuit is configured to store the second information in a second bit. The second circuit is configured to cause the first storage circuit to output the first bits when a value of a least significant bit of the first bits matches a value of the second information stored in the second s