US-12626776-B2 - Semiconductor memory device

US12626776B2US 12626776 B2US12626776 B2US 12626776B2US-12626776-B2

Abstract

A semiconductor memory device includes an error bit detection unit and a bit counting unit. The error bit detection unit detects whether each bit in read data and each bit in expected data of the semiconductor memory device are consistent, and outputs the error bit data indicating pass/error information. The pass/error information indicates whether each detected bit is consistent. The bit counting unit counts the number of error bits in the error bit data indicating an inconsistency between the read data and the expected data, or counts the number of pass bits in the error bit data indicating consistency between the read data and the expected data. Furthermore, the semiconductor memory device also includes an interface for a read operation to input external expected values and an interface for the read operation interfaces to output the number of error bits or pass bits instead of the read data.

Inventors

Yutaka Ito
Hitoshi Ikeda

Assignees

WINBOND ELECTRONICS CORP.

Dates

Publication Date: 20260512
Application Date: 20240418
Priority Date: 20230420

Claims (20)

1 . A semiconductor memory device, comprising: an error bit detection unit, configured to detect whether each bit in read data and each bit in expected data of the semiconductor memory device are consistent, and configured to output error bit data that provides pass/error information, wherein each bit of the pass/error information is generated by a respective bitwise comparison circuit that receives one bit of the expected data and a corresponding bit of the read data, thereby causing each bit position of the pass/error information to indicate, on a one-to-one basis, whether a corresponding detected bit of the read data is consistent with the expected data; and a bit counting unit, configured to count a number of error bits in the error bit data that indicates that the read data and the expected data are inconsistent, or a number of pass bits in the error bit data that indicates that the read data and the expected data are consistent.
2 . The semiconductor memory device as claimed in claim 1 , wherein the error bit detection unit comprises: XOR gate groups, configured to generate the error bit data by performing a XOR operation in bits on the read data and the expected data.
3 . The semiconductor memory device as claimed in claim 2 , further comprising: an expected data preparation unit, configured to prepare write data corresponding to the read data as the expected data, wherein the write data is data written into the semiconductor memory device.
4 . The semiconductor memory device as claimed in claim 3 , wherein the expected data preparation unit inverts a logic level of a bit in the write data that is consistent with an inverted logic level of a bit in the read data as the expected data.
5 . The semiconductor memory device as claimed in claim 3 , wherein the expected data preparation unit latches the write data to compare the write data with the read data.
6 . The semiconductor memory device as claimed in claim 1 , wherein the bit counting unit further comprises: a plurality of sub-error bit counters, each of which is configured to count a number of error bits in partial error bit data assigned to the sub-error bit counter itself among the error bit data, and to output a count value as a partial number of error bits; and an adder, configured to add up the partial number of error bits to obtain the number of error bits.
7 . The semiconductor memory device as claimed in claim 6 , wherein each of the plurality of sub-error bit counters comprises: a first block, configured to obtain a logical product of all bits in the partial error bit data assigned to the sub-error bit counter of the first block itself, and to output a bit indicating the logical product as a highest bit of binary data indicating the partial number of error bits; a second block, configured to generate a voltage corresponding to the partial number of error bits that is assigned to the sub-error bit counter of the second block itself as a reference voltage; a third block, configured to obtain a comparison result between the reference voltage and a voltage corresponding to a bit weight of the third block itself assigned to the binary data, and to output the comparison result as a second highest bit of the binary data indicating the partial number of error bits; and at least one fourth block, configured to obtain a comparison result of the reference voltage and a voltage determined by a value with one or more bits that are higher bits than a bit weight of the at least one fourth block itself assigned to the binary data and a bit of the at least one fourth block itself assigned to the binary data, and to output the comparison result as a bit assigned to the at least one fourth block itself, wherein the bit assigned to the at least one fourth block itself is a third highest bit of the binary data indicating the partial number of error bits.
8 . The semiconductor memory device as claimed in claim 7 , wherein each of the plurality of sub-error bit counters comprises: a device, configured to stop operations of the third block and the at least one fourth block when a value of the highest bit of the binary data indicating the partial number of error bits is the same as a value obtained when the partial number of error bits is maximum.
9 . The semiconductor memory device as claimed in claim 1 , wherein the bit counting unit comprises: a bit counting differential amplifier, configured to input each bit of measurement object data including a plurality of bits and each bit of reference data including a plurality of bits, and to output a determination result (magnitude data) indicating a magnitude relationship between a number of bits in the measurement object data with a first logic level and a number of bits in the reference data with the first logic level; a measurement object data setting unit, configured to provide the error bit data as the measurement object data to the bit counting unit; a reference data setting unit, configured to set logic levels of bits in a reference activation bit number among the plurality of bits in the reference data to the first logic level; and a calculation unit, wherein through a binary search algorithm and an output from the bit counting differential amplifier, the calculation unit is configured to make the reference activation bit number gradually change, and simultaneously to make the bit counting differential amplifier, the measurement object data setting unit, and the bit counting differential amplifier work to obtain the number of error bits from a plurality of magnitude data that are gradually output by the bit counting differential amplifier.
10 . The semiconductor memory device as claimed in claim 9 , wherein the bit counting unit further comprises: a bit correction unit, configured to input the number of error bits obtained by the calculation unit as an uncorrected error bit number, wherein the uncorrected error bit number is directly output as a corrected error bit number if the uncorrected error bit number is the same as the number of error bits in the error bit data, else a number obtained by performing a correction operation on the uncorrected error bit number is output as the corrected error bit number.
11 . The semiconductor memory device as claimed in claim 10 , wherein the bit correction unit: determines whether to execute the correction operation or not based on consistency/inconsistency between a parity of the uncorrected error bit number and a parity of the number of error bits included in the error bit data; and sets the corrected error bit number to a value that differs by only 1 from the uncorrected error bit number in the correction operation.
12 . The semiconductor memory device as claimed in claim 9 , wherein: when the number of error bits included in the error bit data is more than a specific number, the measurement object data setting unit provides the uncorrected error bit number to the bit counting differential amplifier as the measurement object data, so that the number of error bits does not reach the specific number; and the calculation unit determines the number of error bits based on the specific number and a plurality of outputs that are sequentially output from the bit counting differential amplifier.
13 . The semiconductor memory device as claimed in claim 9 , wherein: the bit counting unit outputs data indicating whether a number of bits in the error bit data with the first logic level is zero or greater than 1 based on a comparison result between the error bit data and the reference data with no bit of the first logical level.
14 . The semiconductor memory device as claimed in claim 9 , wherein: the bit counting unit outputs data indicating whether the number of bits in the error bit data with the first logic level is zero or an even number greater than 1 or an odd number greater than 1 based on the comparison result between the error bit data and the reference data with no bit of the first logical level and a parity of the number of bits in the reference data with the first logic level.
15 . The semiconductor memory device as claimed in claim 1 , further comprising: a plurality of memory banks, each of which includes the error bit detection unit; wherein the bit counting unit is a unit that is external to the plurality of memory banks.
16 . The semiconductor memory device as claimed in claim 1 , comprising: a plurality of memory banks; wherein the bit detection unit and the bit counting unit are units external to the plurality of memory banks.
17 . The semiconductor memory device as claimed in claim 1 , wherein: the bit counting unit further comprises a bit counting time generation unit and a bit counting tree unit, the bit counting time generation unit generates a signal for operating the bit counting tree unit, the bit counting tree unit inputs the error bit data, and outputs a determined error bit number.
18 . The semiconductor memory device as claimed in claim 17 , wherein: the bit counting tree unit is configured to count a number of error bits having a predetermined logic level in the error bit data, and to output the determined error bit number in binary.
19 . A semiconductor memory device, comprising: an error bit detection unit, configured to detect whether each bit in read data and each bit in expected data of the semiconductor memory device are consistent, and configured to output error bit data that provides pass/error information, wherein the pass/error information indicates whether each detected bit is consistent; a bit counting unit, configured to count a number of error bits in the error bit data that indicates that the read data and the expected data are inconsistent, or a number of pass bits in the error bit data that indicates that the read data and the expected data are consistent; and a bit counting differential amplifier, configured to input each bit of measurement object data including a plurality of bits and each bit of reference data including a plurality of bits, and to output a determination result (magnitude data) indicating a magnitude relationship between a number of bits in the measurement object data with a first logic level and a number of bits in the reference data with the first logic level.
20 . The semiconductor memory device as claimed in claim 19 , wherein: a measurement object data setting unit, configured to provide the error bit data as the measurement object data to the bit counting unit; a reference data setting unit, configured to set logic levels of bits in a reference activation bit number among the plurality of bits in the reference data to the first logic level; and a calculation unit, wherein through a binary search algorithm and an output from the bit counting differential amplifier, the calculation unit is configured to make the reference activation bit number gradually change, and simultaneously to make the bit counting differential amplifier, the measurement object data setting unit, and the bit counting differential amplifier work to obtain the number of error bits from a plurality of magnitude data that are gradually output by the bit counting differential amplifier.

Description

CROSS REFERENCE TO RELATED APPLICATIONS This application claims priority of Japanese Patent Application No. 2023-069097, filed on Apr. 20, 2023, the entirety of which is incorporated by reference herein. BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to semiconductor memory devices. Description of the Related Art In semiconductor memory devices, write data and read data are often inconsistent due to errors in their physical characteristics. Therefore, it is necessary to obtain relevant information about inconsistent data and to analyze or correct the semiconductor memory device accordingly. For example, an error bit counting device is configured to count the number of inconsistent bits (error bits) between the write data and the read data. Patent document (Japanese Patent Application Publication No. 9-33615) discloses a memory defect analysis device (a semiconductor memory test device). The defective memory is divided into a plurality of blocks to shorten the amount of time required for error counting. Error bits are counted externally of the semiconductor memory, which is the target to be analyzed. However, depending on the situation, the memory defect analysis device is not able to obtain pass/error information of all bits of the semiconductor memory. In view of the above problem, the present invention is intended to provide a semiconductor memory device that includes an error bit counting device. BRIEF SUMMARY OF THE INVENTION A semiconductor memory device includes an error bit detection unit and a bit counting unit. The error bit detection unit detects whether each bit in read data and each bit in expected data of the semiconductor memory device are consistent, and outputs the error bit data indicating pass/error information. The pass/error information indicates whether each detected bit is consistent. The bit counting unit counts the number of error bits in the error bit data, which indicates that there is an inconsistency between the read data and the expected data, or counts the number of pass bits in the error bit data, which indicates that there is consistency between the read data and the expected data. BRIEF DESCRIPTION OF THE DRAWINGS The present invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein: FIG. 1 is a block diagram illustrating a semiconductor memory device according to the first embodiment of the present invention. FIG. 2 is a circuit diagram illustrating the structure of the first half error bit count correlation unit. FIG. 3 is a block diagram illustrating the structure of the second half error bit count correlation unit. FIG. 4 is a time diagram illustrating an example operation of the semiconductor memory device according to the first embodiment of the present invention. FIG. 5 is a block diagram illustrating an example structure #1 of the bit counting unit shown in FIG. 3 and FIG. 17. FIG. 6 is a circuit diagram illustrating the structure of the bit counting tree unit shown in FIG. 5. FIG. 7 shows the adders shown in FIG. 6 FIG. 8 is a circuit diagram of an example structure #1 of the sub-error bit counter shown in FIG. 6. FIG. 9 is a circuit diagram of an example structure #2 of the sub-error bit counter shown in FIG. 6. FIG. 10 is a block diagram of an example structure #2 of the bit counting unit shown in FIG. 3 and FIG. 17. FIG. 11 is a circuit diagram of the structure of the bit comparison unit shown in FIG. 10. FIG. 12 is a circuit diagram of the structure of the bit counting differential amplifier shown in FIG. 11. FIG. 13 is a circuit diagram of the structure of the bit correction unit shown in FIG. 10. FIG. 14 is a time diagram for explaining the operation of the example structure #2 of the bit counting unit shown in FIG. 10. FIG. 15 is a circuit diagram illustrating the structure of the bit count accumulation unit shown in FIG. 3 and FIG. 17. FIG. 16 is a block diagram illustrating a semiconductor memory device according to the second embodiment of the present invention. FIG. 17 is a circuit diagram illustrating a structure of the error bit count correlation unit shown in FIG. 16. DETAILED DESCRIPTION OF THE INVENTION First Embodiment FIG. 1 is a block diagram illustrating a semiconductor memory device 100A according to the first embodiment of the present invention. The semiconductor memory device 100A is a dynamic memory. Referring to FIG. 1, the semiconductor memory device 100A includes an instruction input buffer 801, an instruction decoder 803, an address input buffer 805, an address decoder 807, a DQ input and output buffer 809, a global input and output gate 811, a clock input buffer 813, an internal clock generation unit 815, a mode register and fuse ROM unit 817 and an internal power generation unit 819. In addition, the semiconductor memory device 100A includes memory banks 821-1˜821-n. Each memory bank 821-i (i=1, 2, 3 . .