US-12626777-B2 - Semiconductor memory device

US12626777B2US 12626777 B2US12626777 B2US 12626777B2US-12626777-B2

Abstract

A memory device includes memory cells, first wirings extending along a first direction and connected to the cells, second wirings extending along a second direction and connected to the cells, the second direction intersecting the first direction, third wirings extending along a third direction and each connected to one or more second wirings, the third direction intersecting the first and second directions, sense circuits each connected to one or more third wirings, a switching circuit connected to the circuits and selectively outputting signals from the sense circuits, and a control circuit storing first addresses indicating second and third wirings connected to defective cells, and when a memory cell is selected, determining second addresses indicating second and third wirings connected to the selected cell, and based on the first and second addresses, controlling the switching circuit not to output signals from one or more sense circuits connected to the defective cells.

Inventors

Takeshi Aoki
Masaharu Wada
Mamoru ISHIZAKA

Assignees

KIOXIA CORPORATION

Dates

Publication Date: 20260512
Application Date: 20240710
Priority Date: 20230710

Claims (20)

1 . A semiconductor memory device, comprising: a cell array including a plurality of memory cells; a plurality of first wirings extending along a first direction and connected to the memory cells; a plurality of second wirings extending along a second direction and connected to the memory cells, the second direction intersecting the first direction; a plurality of third wirings extending along a third direction and each connected to one or more of the second wirings, the third direction intersecting the first and second directions; a plurality of sense circuits each connected to one or more of the third wirings; a switching circuit connected to the sense circuits and through which signals from the sense circuits are selectively output; and a control circuit configured to: store first addresses indicating second and third wirings that are connected to defective memory cells, and when a first memory cell is selected for a read operation, determine second addresses indicating second and third wirings that are connected to the first memory cell, and based on the first and second addresses, control the switching circuit so as not to output signals from one or more first sense circuits that are connected to the defective memory cells via the second and third wirings.
2 . The semiconductor memory device according to claim 1 , wherein the switching circuit includes a plurality of switching elements, each of which is switchable to connect to one of two sense circuits that are adjacent to each other, the switching elements including a first switching element that is switchable between one of the first sense circuits and another sense circuit, and the control circuit outputs a control signal to control the switching circuit, the control signal causing the first switching element to switch from said one of the first sense circuits to said another sense circuit.
3 . The semiconductor memory device according to claim 2 , wherein the sense circuits are arranged from one side to another side along the first direction, and each of the switching elements is connected to one of the two sense circuits closer to said one side, before the control signal is output, and the control signal causes one or more of the switching elements closer to said another side than the first switching element to switch to the other of the two sense circuits.
4 . The semiconductor memory device according to claim 3 , wherein the control signal indicates a sequence of bits each corresponding to one of the switching elements, and two or more of the bits corresponding to the first switching element and said one or more of the switching elements are inverted with respect to the other bits.
5 . The semiconductor memory device according to claim 3 , wherein the control circuit includes: a memory that stores the first addresses indicating the second and third wirings that are connected to the defective memory cells, a multiplexer connected to the memory and by which one of the first addresses indicating one of the third wirings that is connected to the defective memory cell via the second wiring is selectively output using an address indicating one of the first wirings connected to the first memory cell, a decoder connected to the multiplexer and by which said one of the first addresses that is output from the multiplexer is converted into first data such that the first data indicates one of the switching elements connected to one of the sense circuits corresponding to said one of the first addresses, a latch circuit connected to the decoder for latching the first data, and a shift circuit connected to the latch circuit and by which the control signal is generated, the control signal causing said one of the switching elements indicated by the first data and other switching elements closer to said another side than said one of the switching elements to switch.
6 . The semiconductor memory device according to claim 5 , further comprising: a gate circuit between the latch circuit and the shift circuit, wherein the memory stores validity information indicating an existence of a defective memory cell for each of the second wirings, and the gate circuit outputs the first data latched by the latch circuit to the shift circuit based on the validity information.
7 . The semiconductor memory device according to claim 3 , wherein the control circuit includes: a memory that stores the first addresses indicating the second and third wirings that are connected to the defective memory cells, a decoder connected to the memory and by which one or more of the first addresses indicating the third wirings that are connected to the defective memory cells are converted into one or more pieces of second data such that the pieces of second data respectively indicate the switching elements connected to the sense circuits corresponding to said one or more of the first addresses, a latch circuit connected to the decoder for latching the pieces of second data, a multiplexer connected to the latch circuit and by which one of the pieces of second data corresponding to one of the third wirings connected to the defective memory cell via the second wiring is selectively output using an address indicating one of the first wirings connected to the first memory cell, and a shift circuit connected to the multiplexer and by which the control signal is generated, the control signal causing one of the switching elements indicated by said one of the pieces of second data and other switching elements closer to said another side than said one of the switching elements to switch.
8 . The semiconductor memory device according to claim 7 , further comprising: a gate circuit between the multiplexer and the shift circuit, wherein the memory stores validity information indicating an existence of a defective memory cell for each of the second wirings, and the gate circuit outputs said one of the pieces of second data to the shift circuit based on the validity information.
9 . The semiconductor memory device according to claim 2 , wherein each of the switching elements is connected in series between two sense circuits that are adjacent to each other.
10 . The semiconductor memory device according to claim 9 , wherein each of the switching elements includes two transistors that are respectively connected to the two sense circuits and operate in a way complementary to each other such that a signal from either one of the two sense circuits is output from a node between the two transistors.
11 . The semiconductor memory device according to claim 1 , wherein the cell array is a three-dimensional memory cell array.
12 . The semiconductor memory device according to claim 1 , wherein each of the memory cells includes: a first transistor including a source, a drain, and a gate that is connected to one of the first wirings, one of the source and the drain being connected to one of the second wirings, and a first capacitor connected to the other of the source and the drain of the first transistor.
13 . The semiconductor memory device according to claim 1 , wherein each of the memory cells is disposed at an intersection of one of the first wirings and one of the second wirings, and one end of each of the second wirings is connected to one of the third wirings.
14 . The semiconductor memory device according to claim 1 , wherein in response to the read operation, a data signal is conveyed by one of the third wirings, and a reference signal to be used to detect the data signal is conveyed by another of the third wirings.
15 . The semiconductor memory device according to claim 1 , wherein each of the sense circuits is connected to one pair of the third wirings that are adjacent to each other.
16 . The semiconductor memory device according to claim 1 , wherein each of the sense circuits is connected to one pair of the third wirings, and is between the one pair of the third wirings.
17 . The semiconductor memory device according to claim 1 , further comprising: a plurality of fourth wirings extending along the third direction and arranged along the second direction, each of the fourth wirings being connected to one or more of the first wirings, wherein the cell array includes a plurality of memory cell layers corresponding to the fourth wirings.
18 . The semiconductor memory device according to claim 17 , further comprising: a plurality of second transistors disposed at ends of the first wirings, wherein the fourth wirings are connected to gates of the second transistors.
19 . The semiconductor memory device according to claim 1 , further comprising: a plurality of third transistors disposed at ends of the second wirings, wherein the third wirings are connected to the second wirings via the third transistors.
20 . The semiconductor memory device according to claim 1 , further comprising: a controller configured to output to the control circuit an address indicating one of the first wirings connected to the first memory cell, wherein the control circuit determines the second addresses using the address that is output by the controller.

Description

CROSS-REFERENCE TO RELATED APPLICATION(S) This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2023-113315, filed Jul. 10, 2023, the entire contents of which are incorporated herein by reference. FIELD Embodiments described herein relate generally to a semiconductor memory device. BACKGROUND A semiconductor memory device such as a dynamic random access memory (DRAM), in which memory cells are arrayed three-dimensionally, is being developed. In order to reduce a bit line capacity and thereby secure an improved sensing margin, a three-dimensional memory cell array has a hierarchical bit line structure such that bit lines are tiered in global bit lines and local bit lines. In this kind of memory cell array, when a defective cell appears, the defective cell needs to be replaced with or rescued by a redundant cell. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic perspective view showing a configuration of a semiconductor memory device according to a first embodiment. FIG. 2 is a perspective view showing one bit line and a configuration of a periphery thereof. FIG. 3 is a block diagram showing a configuration of the semiconductor memory device according to the first embodiment. FIG. 4 through FIG. 6 are conceptual drawings showing an example of a configuration and an example of an operation of a switching circuit. FIG. 7 is a circuit diagram showing an example of a configuration of a switch element. FIG. 8 is a conceptual drawing showing an example of a configuration and an example of an operation of a switch control circuit. FIG. 9 is a block diagram showing an example of a gate circuit. FIG. 10 is a block diagram showing an example of a shift circuit. FIG. 11 is a conceptual drawing showing an example of a configuration and an example of an operation of the switch control circuit according to a second embodiment. FIG. 12 is a schematic plan view showing an example of a bit line disposition. FIG. 13 is a schematic plan view showing another example of a bit line disposition. DETAILED DESCRIPTION Embodiments provide a semiconductor memory device such that even when a defective cell appears, the defective cell can be reliably replaced with a redundant cell. In general, according to one embodiment, a semiconductor memory device, comprises a cell array including a plurality of memory cells; a plurality of first wirings extending along a first direction and connected to the memory cells; a plurality of second wirings extending along a second direction and connected to the memory cells, the second direction intersecting the first direction; a plurality of third wirings extending along a third direction and each connected to one or more of the second wirings, the third direction intersecting the first and second directions; a plurality of sense circuits each connected to one or more of the third wirings; a switching circuit connected to the sense circuits and through which signals from the sense circuits are selectively output; and a control circuit configured to: store first addresses indicating second and third wirings that are connected to defective memory cells, and when a first memory cell is selected for a read operation, determine second addresses indicating second and third wirings that are connected to the first memory cell, and based on the first and second addresses, control the switching circuit so as not to output signals from one or more first sense circuits that are connected to the defective memory cells via the second and third wirings. First Embodiment FIG. 1 is a schematic perspective view showing a configuration of a semiconductor memory device 1 according to a first embodiment. The semiconductor memory device 1 of the present embodiment is, for example, a DRAM including a three-dimensional memory cell array MCA in which memory cells MC are arrayed three-dimensionally. The memory cell MC is used as a memory cell in which one-bit data or multibit data are stored. Multiple memory cells MC are arrayed two-dimensionally in a matrix form in an X-Y plane, configuring one memory cell layer LYR. Also, a memory cell array MCA includes multiple memory cell layers LYR being stacked in a Z direction. The multiple memory cell layers LYR are stacked approximately parallel to each other in the memory cell array MCA. Because of this, the multiple memory cells MC are arrayed three-dimensionally. The semiconductor memory device 1 according to the present embodiment includes the memory cell array MCA, multiple word lines WL, multiple bit lines VBL, multiple global bit lines GBL, multiple bit line select transistors Tbls, and multiple memory cell layer select transistors Tlys and bTlys. The word lines WL extend in the X direction in the plane of the memory cell layer LYR, and are connected to the memory cells MC arrayed in the X direction. The word lines WL are arrayed in the Y direction in the memory cell layer LYR. One end of the word lines WL is connected to a