US-12627042-B2 - Phased array transceiver with built-in phase interferometer and/or transmitter linearization feedback

Abstract

Methods and devices for streamlining phase and amplitude calibration and linearization in RF transceiver circuits including a plurality of switchable transmit and receive processing paths is presented. According to one aspect, switchable feedback paths are provided that can selectively feedback a portion of a transmitted RF signal or a test RF signal for use in the calibration. According to another aspect, the switchable feedback paths include combination of switches and couplers to selectively combine feedback from one or more of the switchable feedback paths. According to another aspect, the switchable feedback paths reuse portions of the receive paths of the plurality of switchable transmit and receive processing paths. The switchable feedback paths can be used to provide a combined feedback RF signal based on one or more transmitted RF signals that can be used as a digital pre-distortion feedback for linearization of the one or more transmitted RF signals.

Inventors

• Donald Felt Kimball
• Carl Einer TULBERG
• Bautista REINOSO

Assignees

• MURATA MANUFACTURING CO., LTD.

Dates

Publication Date

20260512

Application Date

20240718

Claims (20)

1. 1 . A transceiver circuit comprising: a plurality of RF transmit paths for transmission of a plurality of respective RF signals through a plurality of respective elements of an antenna array; a plurality of RF receive paths for reception of a plurality of respective RF signals through the plurality of respective elements of the antenna array; and an RF combiner circuit selectively coupled to the plurality of RF transmit paths and/or to the plurality of RF receive paths, wherein during a transmit path linearization mode of operation, i) one or more RF transmit paths of the plurality of RF transmit paths are coupled to the respective elements of the antenna array, and ii) the RF combiner circuit is configured to combine portions of the respective RF signals through the one or more RF transmit paths into a combined RF signal that is configured to be used by a controller for linearization of the one or more RF transmit paths.
2. 2 . The transceiver circuit according to claim 1 , wherein the RF combiner circuit comprises a plurality of RF combiners selectively coupled to the plurality of RF transmit paths and/or to the plurality of RF receive paths via a plurality of switches.
3. 3 . The transceiver circuit according to claim 1 , wherein the RF combiner circuit comprises a plurality of bidirectional signal paths that are selectively coupled to the plurality of RF transmit paths and/or to the plurality of RF receive paths.
4. 4 . The transceiver circuit according to claim 3 , wherein during the transmit path linearization mode of operation, the one or more RF transmit paths are coupled to one or more of the plurality of bidirectional signal paths, and wherein during a reception mode of operation, one or more of the plurality of RF receive paths are coupled to the one or more of the plurality of bidirectional signal paths.
5. 5 . The transceiver circuit according to claim 1 , wherein the combined RF signal is used by the controller as a pre-distortion feedback to a single input single output (SISO) digital pre-distortion algorithm.
6. 6 . The transceiver circuit according to claim 5 , wherein the transceiver circuit further comprises a mixer circuit, and wherein in the transmit path linearization mode, i) an input of the mixer circuit is coupled to the combined RF signal that is used as the pre-distortion feedback, and ii) the mixer circuit generates a down converted signal corresponding to the combined RF signal for use by the controller.
7. 7 . The transceiver circuit according to claim 6 , wherein based on the down converted signal, the SISO digital pre-distortion algorithm generates pre-distortion components that are used to generate a pre-distorted transmit data signal for transmission through the one or more RF transmit paths that are coupled to the respective elements of the antenna array.
8. 8 . The transceiver circuit according to claim 7 , wherein the pre-distorted transmit data signal is up converted by the mixer prior to the transmission.
9. 9 . The transceiver circuit according to claim 1 , wherein the one or more RF transmit paths comprises a plurality of transmit paths arranged as different groups of transmit paths.
10. 10 . The transceiver circuit according to claim 9 , wherein each group of the different groups of transmit paths forms a respective combined emitted RF beam through a respective group of elements of the antenna array according to a respective substantially same elevation or azimuth.
11. 11 . The transceiver circuit according to claim 10 , wherein the respective group of elements of the antenna arrays form a row or a column of the antenna array.
12. 12 . The transceiver circuit according to claim 10 , wherein the different groups of transmit paths are linearized through the transmit path linearization mode at a different time.
13. 13 . The transceiver circuit according to claim 1 , wherein each RF receive path of the plurality of RF receive paths is configured to adjust a phase or an amplitude of the respective RF signal received through the respective element of the antenna array.
14. 14 . The transceiver circuit according to claim 1 , wherein each RF transmit path of the one or more RF transmit paths is configured to adjust a phase or an amplitude of the respective RF signal for transmission through the respective element of the antenna array.
15. 15 . The transceiver circuit according to claim 14 , wherein each RF transmit path of the one or more RF transmit paths comprises an amplifier that is configured to output a phase and amplitude adjusted RF signal, and wherein the RF combiner circuit further comprises: a power coupler that is coupled to an output of the amplifier, the power coupler configured to generate from the output of the amplifier the portion of the phase and amplitude adjusted RF signal; and a first switch that is coupled via a common pole of the first switch to a terminal of the power coupler that carries the portion of the phase and amplitude adjusted RF signal.
16. 16 . The transceiver circuit according to claim 15 , further comprising: an antenna switch that is configured to selectively couple a same element of the plurality elements of the antenna array to a respective RF transmit path or to a respective RF receive path.
17. 17 . The transceiver circuit according to claim 1 , wherein the plurality of RF transmit paths and RF receive paths are grouped in pairs according to a first polarization and a second polarization, and wherein the transmit path linearization mode for RF transmit paths associated to the first polarization is independent from the transmit path linearization mode for RF transmit paths associated to the second polarization.
18. 18 . The transceiver circuit according to claim 17 , wherein the transmit path linearization mode for RF transmit paths associated to the first polarization is enabled concurrently with the transmit path linearization mode for RF transmit paths associated to the second polarization.
19. 19 . The transceiver circuit according to claim 1 , wherein transistors of the transceiver circuit comprise metal-oxide-semiconductor (MOS) field effect transistors (FETs).
20. 20 . The transceiver circuit according to claim 19 , wherein said transistors are fabricated using one of: a) silicon-on-insulator (SOI) technology, b) silicon-on-sapphire (SOS) technology, and c) bulk silicon (Si) technology.

Description

CROSS REFERENCE TO RELATED APPLICATIONS The present application is a continuation application of U.S. application Ser. No. 17/558,106 filed on Dec. 21, 2021, which is incorporated herein by reference in its entirety and is a continuation application of PCT application PCT/US2020/039173 filed on Jun. 23, 2020, the disclosure of which is incorporated herein by reference in its entirety, which PCT application is, in turn, a continuation in part application of i) U.S. application Ser. No. 16/455,517 filed on Jun. 27, 2019 and issued as U.S. Pat. No. 10,965,026 on Mar. 30, 2021, the disclosure of which is also incorporated herein by reference in its entirety and ii) U.S. application Ser. No. 16/601,302 filed on Oct. 14, 2019 and issued as U.S. Pat. No. 10,715,199 on Jul. 14, 2020, the disclosure of which is also incorporated herein by reference in its entirety. U.S. application Ser. No. 16/601,302 is, in turn, a continuation application of U.S. application Ser. No. 16/455,427 filed on Jun. 27, 2019 and issued as U.S. Pat. No. 10,484,038 on Nov. 19, 2019, the disclosure of which is also incorporated herein by reference in its entirety. The present application may also be related to U.S. Pat. No. 9,717,008, entitled “Integrated Circuit Calibration Architecture”, issued Jul. 25, 2017, the disclosure of which is incorporated herein by reference in its entirety. TECHNICAL FIELD The present teachings relate to RF (radio frequency) circuits. More particularly, the present teachings relate to methods and apparatuses for streamlining phase and amplitude calibration and linearization in RF transceiver circuits that can be used in beam forming and/or steering applications. BACKGROUND The advent of next-generation 5G standard for millimeter-wave cellular communication has pushed the design of hybrid multiple-input multiple-output (MIMO) transceiver systems for interfacing with antenna array to provide directional signal transmission or reception. Signal processing techniques, such as beam forming or beam steering that can provide for the necessary spatial filtering, are implemented by a combination of digital and analog circuit blocks in the transceiver systems. Such transceiver systems may be based on time division duplex (TDD) mode of operation where transmission and reception are performed via a plurality of transmit paths and receive paths that operate at a same frequency but are activated at different time slots. Performance in beam forming/steering may be dependent on accuracy by which the transceiver can generate phase and amplitude information to the many elements of the antenna array, and/or on accuracy by which the transceiver can extract phase and amplitude information from the many elements of the antenna array. Accordingly, calibration of a phase and amplitude adjustment block in the plurality of transmit and receive paths of the transceiver becomes a requirement, especially in mass production environments where wider tolerances in lower cost standard components may invariably introduce performance variation. Some challenges associated with calibration of the transceiver include the high number of ports from/to which test signals must be read/injected, as well as the millimeter-wave nature of signals of interest. Description of some such challenges and implementation examples can be found, for example, in the above referenced U.S. Pat. No. 9,717,008. Furthermore, it may be desirable to reduce built-in test circuits related to the calibration, as such test circuits may not only increase a physical size of the transceiver but may also introduce undesired couplings between the different transmit and receive paths of the transceiver. Such couplings in turn may affect performance of the beam forming/steering, including in applications where (patch) elements of the antenna are fed with (horizontal and vertical) polarized RF signals. Furthermore, requirements for higher power output from power amplifiers (PAS) used in transmit paths of transceivers that are used in, for example, base stations, may require the PAs to operate away from the power back-off condition (e.g., linear region). Accordingly, any such PAs may operate in a non-linear region (i.e., saturation) with resulting output phase and amplitude distortion that may negatively affect performance of the PA in exchange for higher output power and efficiency of the PA. Such trade-off between efficiency and linearity has been neutralized by current digital pre-distortion (DPD) schemes which may realize a linear response of a combined DPD and PA block by cascading the PA and its inverse block. As can be taken from the related references [1] and [2], which are incorporated herein by reference in their entirety, such DPD schemes may require a separate feedback path from the output of each PA, and therefore from each transmit path, to an input of a digital signal processor implementing the DPD functionality. It would be clear to a person skilled in the art that such f