US-12627138-B2 - Electrical discharge circuit

US12627138B2US 12627138 B2US12627138 B2US 12627138B2US-12627138-B2

Abstract

The present disclosure discloses an electrical discharge circuit. A voltage-dividing circuit performs voltage division on a voltage input terminal such that a detection circuit generates a boosted detection signal accordingly. A first inverter is coupled to a first voltage feeding terminal and a second inverter input terminal. A second inverter is coupled to a first inverter output terminal and a ground terminal. An inverter control circuit boosts the boosted detection circuit to generate an inverted control signal to a first inverter input terminal. A first switch circuit is coupled to one of the first and the second inverter terminals and the ground terminal. The boosted detection signal turns on and turns off the first and the second switch circuits respectively when an ESD input occurs such that a first and a second discharge transistors controlled by the inverter output terminals turn on to discharge the voltage input terminal.

Inventors

Chung-Yu Huang

Assignees

REALTEK SEMICONDUCTOR CORPORATION

Dates

Publication Date: 20260512
Application Date: 20240311
Priority Date: 20230324

Claims (11)

1 . An electrical discharge circuit, comprising: a voltage-dividing circuit electrically coupled to a voltage input terminal to generate a detection signal at a voltage-dividing terminal, wherein the voltage input terminal is electrically coupled to a first voltage feeding terminal that has a first voltage feeding thereto; a detection circuit configured to operate according to a second voltage smaller than the first voltage to perform voltage-boost on the detection signal to generate a boosted detection signal; a first inverter having a first inverter input terminal and a first inverter output terminal and electrically coupled between the first voltage feeding terminal and a second inverter input terminal; a second inverter having the second inverter input terminal and a second inverter output terminal and electrically coupled between the first inverter output terminal and a ground terminal; an inverter control circuit configured to operate according to the first voltage to boost the boosted detection signal to generate a control signal inverted to the boosted detection signal to the first inverter input terminal; a first switch circuit electrically coupled between the ground terminal and one of the first inverter input terminal and second inverter input terminal; a second switch circuit electrically coupled between a second voltage feeding terminal that has a second voltage feeding thereto and the second inverter input terminal; and a first discharge transistor and a second discharge transistor electrically coupled in series between the first voltage feeding terminal and the ground terminal, wherein the first discharge transistor is controlled by a first voltage of the first inverter output terminal, and the second discharge transistor is controlled by the second voltage of the second inverter output terminal; wherein when an ESD input occurs at the voltage input terminal, the boosted detection signal turns on the first switch circuit and turns off the second switch circuit such that the first discharge transistor and the second discharge transistor are turned on to discharge the voltage input terminal.
2 . The electrical discharge circuit of claim 1 , wherein the inverter control circuit comprises: a first voltage input circuit and a second voltage input circuit each comprising: a first N-type input transistor electrically coupled between an input node and a first internal node and controlled by the second voltage; a second N-type input transistor electrically coupled between the first internal node and a second internal node and controlled by a voltage of a third internal node; a first P-type input transistor electrically coupled between the second internal node and an output node and controlled by the second voltage; a second P-type input transistor electrically coupled between the second voltage feeding terminal and the output node and controlled by a voltage of the second internal node; a first P-type control transistor electrically coupled between the second internal node and the third internal node and controlled by the second voltage; and a second P-type control transistor electrically coupled between the second voltage feeding terminal and the third internal node and controlled by the voltage of the second internal node; and a voltage output circuit comprising: a first P-type output transistor electrically coupled between the first voltage feeding terminal and the output node of the first voltage input circuit, and controlled by a voltage of the output node of the second voltage input circuit; and a second P-type output transistor electrically coupled between the first voltage feeding terminal and the output node of the second voltage input circuit, and controlled by a voltage of the output node of the first voltage input circuit; wherein the input node of the first voltage input circuit is configured to receive the boosted detection signal, the input node of the second voltage input circuit is configured to receive an inverted boosted detection signal which is inverted to the boosted detection signal, and the output node of the second voltage input circuit to generate the control signal.
3 . The electrical discharge circuit of claim 1 , wherein the detection circuit comprises: a first detection inverter configured to receive and invert the detection signal to generate an inverted detection signal; a second detection inverter configured to receive and invert the inverted detection signal to generate an output detection signal; and a voltage-boost circuit comprising: a first P-type transistor and a second P-type transistor, wherein the first P-type transistor has a first P-type transistor control terminal, and the second P-type transistor has a second P-type transistor control terminal; a first P-type transistor circuit and a first N-type transistor circuit electrically coupled in series between the first P-type transistor and the ground terminal through a first terminal and electrically coupled to the second voltage feeding terminal through the first P-type transistor, each of the first P-type transistor circuit and the first N-type transistor circuit has a first control terminal configured to receive the output detection signal; and a second P-type transistor circuit and a second N-type transistor circuit electrically coupled in series between the second P-type transistor and the ground terminal through a second terminal and electrically coupled to the second voltage feeding terminal through the second P-type transistor, each of the second P-type transistor circuit and the second N-type transistor circuit has a second control terminal configured to receive the inverted detection signal; wherein the first P-type transistor control terminal is electrically coupled to the second terminal, the second P-type transistor control terminal is electrically coupled to the first terminal, the second terminal is configured to generate the boosted detection signal, and the first terminal is configured to generate the inverted boosted detection signal.
4 . The electrical discharge circuit of claim 3 , wherein the first detection inverter and the second detection inverter operate according to a third voltage feeding terminal that has a third voltage feeding thereto, wherein the third voltage is smaller than the second voltage.
5 . The electrical discharge circuit of claim 3 , further comprising a feedback transistor electrically coupled between the ground terminal and a connection terminal which is between the first detection inverter and the second detection inverter and controlled by the boosted detection signal or a voltage of the second inverter output terminal to decrease a transition speed of the voltage-boost circuit.
6 . The electrical discharge circuit of claim 1 , wherein the first switch circuit comprises a first N-type switch transistor and a second N-type switch transistor electrically coupled in series, wherein the first N-type switch transistor is controlled by the second voltage to be turned on, and the second N-type switch transistor is controlled by the boosted detection signal; the second switch circuit comprises a P-type switch transistor and is controlled by the boosted detection signal.
7 . The electrical discharge circuit of claim 1 , wherein under a normal operation mode that a voltage amount of the voltage input terminal does not exceed a predetermined level, the detection signal is at a low state level, and the boosted detection signal is at the low state level such that the first switch circuit turns off to pull high a voltage of the first inverter input terminal, and the second switch circuit turns on to pull high a voltage of the second inverter input terminal; the first inverter further pulls a voltage of the first inverter output terminal to the second voltage to turn off the first discharge transistor, and the second inverter further pull a voltage of the second inverter output terminal to a ground voltage level to turn off the second discharge transistor.
8 . The electrical discharge circuit of claim 1 , wherein under a discharging mode that a voltage amount of the voltage input terminal exceeds a predetermined level due to the ESD input received at the voltage input terminal, the detection signal is at a high state level, and the boosted detection signal is at the high state level such that the first switch circuit turns on to pull low a voltage of the first inverter input terminal, and the second switch circuit turns off to keep the second inverter input terminal floating; the first inverter further pulls a voltage of the first inverter output terminal to the first voltage to turn on the first discharge transistor, and the second inverter pulls a voltage of the second inverter output terminal to the first voltage to turn on the second discharge transistor.
9 . The electrical discharge circuit of claim 1 , further comprising: a power voltage-dividing circuit electrically coupled to a power voltage input terminal configured to transmit a power signal to generate a power detection signal at a power voltage-dividing terminal, wherein the power voltage input terminal is electrically coupled to the first voltage feeding terminal; a power detection circuit comprising a first load circuit, a second load circuit and a detection transistor electrically coupled in series between the second voltage feeding terminal and the ground terminal, the detection transistor is controlled by the power detection signal and generates an inverted power detection signal at a load output terminal between the first load circuit and the second load circuit; and a power detection inverter configured to receive and output the inverted power detection signal as an output power detection signal; wherein when the ESD input occurs at the power voltage input terminal, the output power detection signal turns on the first switch circuit and turns off the second switch circuit such that the first discharge transistor and the second discharge transistor are turned on to discharge the voltage input terminal.
10 . The electrical discharge circuit of claim 9 , further comprising a detection signal output circuit, comprising: a first N-type output transistor electrically coupled between an output node and the ground terminal and controlled by the output power detection signal; a first P-type output transistor and a second P-type output transistor electrically coupled in series between the second voltage feeding terminal and the output node, wherein the first P-type output transistor is controlled by the boosted detection signal, and the second P-type output transistor is controlled by the output power detection signal; a second N-type output transistor electrically coupled between the output node and the ground terminal and controlled by the boosted detection signal; and an output inverter configured to receive and output a voltage of the output node to be an actual detection signal; wherein when the ESD input occurs at the voltage input terminal, the actual detection signal turns on the first switch circuit and turns off the second switch circuit according to the boosted detection signal such that the first discharge transistor and the second discharge transistor are turned on to discharge the voltage input terminal; when the ESD input occurs at the power voltage input terminal, the actual detection signal turns on the first switch circuit and turns off the second switch circuit according to the output power detection signal such that the first discharge transistor and the second discharge transistor are turned on to discharge the voltage input terminal.
11 . An electrical discharge circuit, comprising: a voltage-dividing circuit electrically coupled to a voltage input terminal to generate a detection signal at a voltage-dividing terminal, wherein the voltage input terminal is electrically coupled to a first voltage feeding terminal that has a first voltage feeding thereto; a detection circuit configured to operate according to a second voltage smaller than the first voltage to perform voltage-boost on the detection signal to generate a boosted detection signal; a first inverter having a first inverter input terminal and a first inverter output terminal and electrically coupled between the first voltage feeding terminal and a second inverter input terminal; a second inverter having the second inverter input terminal and a second inverter output terminal and electrically coupled between the first inverter output terminal and a ground terminal; a resistor electrically coupled between the first voltage feeding terminal and the first inverter input terminal; a first switch circuit electrically coupled between the first inverter input terminal and the ground terminal; a second switch circuit electrically coupled between a second voltage feeding terminal that has a second voltage feeding thereto and the second inverter input terminal; and a first discharge transistor and a second discharge transistor electrically coupled in series between the first voltage feeding terminal and the ground terminal, wherein the first discharge transistor is controlled by a first voltage of the first inverter output terminal, and the second discharge transistor is controlled by the second voltage of the second inverter output terminal; wherein when an ESD input occurs at the voltage input terminal, the boosted detection signal turns on the first switch circuit and turns off the second switch circuit such that the first discharge transistor and the second discharge transistor are turned on to discharge the voltage input terminal.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present disclosure relates to an electrical discharge circuit. 2. Description of Related Art Electrostatic discharge (ESD) may cause permanent damage to electronic components and equipments such that the circuit function of the integrated circuit is affected. The products including the damaged components thus cannot operate properly. ESD may occur during the manufacturing, packaging, testing, storing or moving of the chips. In order to recreate and prevent the occurrence of ESD, integrated circuit products may use ESD protection components or circuits to perform testing so as to enhance the protection ability against ESD and further increase the yield of the electronic products. SUMMARY OF THE INVENTION In consideration of the problem of the prior art, an object of the present disclosure is to provide an electrical discharge circuit. The present invention discloses an electrical discharge circuit that includes a voltage-dividing circuit, a detection circuit, a first inverter, a second inverter, an inverter control circuit, a first switch circuit, a second switch circuit, a first discharge transistor and a second discharge transistor. The voltage-dividing circuit is electrically coupled to a voltage input terminal to generate a detection signal at a voltage-dividing terminal, wherein the voltage input terminal is electrically coupled to a first voltage feeding terminal that has a first voltage feeding thereto. The detection circuit is configured to operate according to a second voltage smaller than the first voltage to perform voltage-boost on the detection signal to generate a boosted detection signal. The first inverter has a first inverter input terminal and a first inverter output terminal and is electrically coupled between the first voltage feeding terminal and a second inverter input terminal. The second inverter has the second inverter input terminal and a second inverter output terminal and is electrically coupled between the first inverter output terminal and a ground terminal. The inverter control circuit is configured to operate according to the first voltage to boost the boosted detection signal to generate a control signal inverted to the boosted detection signal to the first inverter input terminal. The first switch circuit is electrically coupled between the ground terminal and one of the first inverter input terminal and second inverter input terminal. The second switch circuit is electrically coupled between a second voltage feeding terminal that has a second voltage feeding thereto and the second inverter input terminal. The first discharge transistor and the second discharge transistor are electrically coupled in series between the first voltage feeding terminal and the ground terminal, wherein the first discharge transistor is controlled by a first voltage of the first inverter output terminal and the second discharge transistor is controlled by a second voltage of the second inverter output terminal. When an ESD input occurs at the voltage input terminal, the boosted detection signal turns on the first switch circuit and turns off the second switch circuit such that the first discharge transistor and the second discharge transistor are turned on to discharge the voltage input terminal. The present invention discloses an electrical discharge circuit that includes a voltage-dividing circuit, a detection circuit, a first inverter, a second inverter, a resistor, a first switch circuit, a second switch circuit, a first discharge transistor and a second discharge transistor. The voltage-dividing circuit is electrically coupled to a voltage input terminal to generate a detection signal at a voltage-dividing terminal, wherein the voltage input terminal is electrically coupled to a first voltage feeding terminal that has a first voltage feeding thereto. The detection circuit is configured to operate according to a second voltage smaller than the first voltage to perform voltage-boost on the detection signal to generate a boosted detection signal. The first inverter has a first inverter input terminal and a first inverter output terminal and is electrically coupled between the first voltage feeding terminal and a second inverter input terminal. The second inverter has the second inverter input terminal and a second inverter output terminal and is electrically coupled between the first inverter output terminal and a ground terminal. The resistor is electrically coupled between the first voltage feeding terminal and the first inverter input terminal. The first switch circuit is electrically coupled between the first inverter input terminal and the ground terminal. The second switch circuit is electrically coupled between a second voltage feeding terminal that has a second voltage feeding thereto and the second inverter input terminal. The first discharge transistor and the second discharge transistor are electrically coupled in series betwee