US-12627212-B2 - Slew-rate control for power stages

Abstract

A circuit includes a half-bridge circuit is configured to provide a switching voltage responsive to respective high-side and low-side drive signals. High-side slew control circuitry is configured to provide a high-side slew-compensated control signal responsive to a high-side enable signal and a slew current signal representative of a slew rate at a switching output. A high-side driver is configured to provide the high-side drive signal responsive to the high-side slew-compensated control signal. Low-side slew control circuitry is configured to provide a low-side slew-compensated drive signal responsive to a low-side enable signal and the slew current signal. A low-side driver is configured to provide the low-side drive signal responsive to the low-side slew-compensated control signal. A capacitor is coupled between the high-side and low-side slew control circuitry and is configured to convert the slew rate to the slew current signal.

Inventors

• Maik Peter Kaufmann
• Stefan Herzer
• Michael Lueders

Assignees

• TEXAS INSTRUMENTS INCORPORATED

Dates

Publication Date

20260512

Application Date

20220929

Claims (20)

1. 1 . A circuit comprising: a driver having a drive input and a drive output; and a control circuitry having a sense terminal and a control output, the sense terminal coupled to a transistor current terminal, the control output coupled to the drive input, the slew-control circuitry configurable to: responsive to a state of the sense terminal indicating a state change of the transistor current terminal, cause the driver to provide a first current at the drive output; and responsive to the state of the sense terminal indicating that the transistor current terminal is in a particular state, cause the driver to provide a second current at the drive output, the second current being lower than the first current.
2. 2 . The circuit of claim 1 , wherein the control circuitry includes: a first switch and a first resistor coupled between a first voltage input and the sense terminal, the first switch having a first switch control input; and a second switch and a second resistor coupled between the sense terminal and the transistor current terminal, the second switch having a second switch control input.
3. 3 . The circuit of claim 2 , wherein the drive input is a first drive input, the driver has a second drive input, the control output is a first control output coupled to the first drive input, the control circuitry has a second control output coupled to the second drive input and includes: a first buffer having a first buffer input and a first buffer output, the first buffer output coupled to the first control output; a third switch coupled between the sense terminal and the first buffer input, the third switch having a third switch control input coupled to the first switch control input; a second buffer having a second buffer input and a second buffer output, the second buffer output coupled to the second control output; and a fourth switch coupled between the sense terminal and the second buffer input, the fourth switch having a fourth control switch input coupled to the second switch control input.
4. 4 . The circuit of claim 3 , wherein the driver comprises: a first current source having a first current control input and a first current output, the first current control input coupled to the first drive input, and the first current output coupled to the drive output; and a second current source having a second current control input and a second current output, the second current control input coupled to the second drive input, and the second current output coupled to the drive output.
5. 5 . The circuit of claim 1 , further comprising a first transistor coupled between a power terminal and a switching terminal, and a second transistor coupled between the switching terminal and a reference terminal, the first transistor having a first control terminal, the second transistor having a second control terminal, wherein the drive output is coupled to one of the first or second control terminals, and the sense terminal is coupled to the switching terminal.
6. 6 . The circuit of claim 5 , wherein the driver is a first driver, the drive input is a first drive input, the drive output is a first drive output coupled to the first control terminal; wherein the control circuitry is a first control circuitry, the sense terminal is a first sense terminal, and the control output is a first control output; wherein the circuit further comprises: a second driver having a second drive input and a second drive output, the second drive output coupled to the second control terminal; and a second control circuitry having a second sense terminal and a second control output, the second sense terminal coupled to the first sense terminal, the second control output coupled to the second drive input, and the second control circuitry configurable to: responsive to a state of the second sense terminal indicating the state change of the transistor current terminal, cause the second driver to provide a third current at the second drive output; and responsive to the state of the second sense terminal indicating that the transistor current terminal is in a particular state, cause the second driver to provide a fourth current at the second drive output, the fourth current being lower than the third current.
7. 7 . The circuit of claim 6 , further comprising a capacitor coupled between the first and second sense terminals.
8. 8 . The circuit of claim 7 , wherein the capacitor has a linear capacitance configurable to translate a slew rate at the first and second drive outputs to a respective current representative of the slew rate.
9. 9 . The circuit of claim 7 , wherein the circuit comprises an integrated circuit die including the capacitor and at least one of the first or second transistors.
10. 10 . The circuit of claim 9 , wherein the integrated circuit die is a first integrated circuit die including the second transistor and the capacitor, and the first transistor, the first driver and the second driver are on a second integrated circuit die.
11. 11 . The circuit of claim 9 , wherein the first transistor, the first driver and the second driver are on the integrated circuit die including the second transistor and the capacitor.
12. 12 . The circuit of claim 5 , wherein the first and second transistors form a half-bridge circuit.
13. 13 . The circuit of claim 1 , wherein the sense terminal is coupled to a capacitor terminal.
14. 14 . The circuit of claim 1 , wherein the sense terminal is coupled to the transistor current terminal via a resistor and a switch.
15. 15 . A circuit comprising: a first transistor coupled between a power terminal and a switching terminal, the first transistor having a first control terminal; a second transistor coupled between the switching terminal and a reference terminal, the second transistor having a second control terminal; a first driver having a first drive input and a first drive output, the first drive output coupled to the first control terminal; a second driver having a second drive input and a second drive output, the second drive output coupled to the second control terminal; a first control circuitry having a first sense terminal and a first control output, the first sense terminal coupled to the switching terminal, and the first control output coupled to the first drive input, the first control circuitry configurable to: responsive to a state of the first sense terminal indicating a state change of the switching terminal, cause the first driver to provide a first current at the first drive output; and responsive to the state of the first sense terminal indicating that the switching terminal is in a particular state, cause the first driver to provide a second current at the first drive output, the second current being lower than the first current; and a second control circuitry having a second sense terminal and a second control output, the second sense terminal coupled to the first sense terminal, and the second control output coupled to the second drive input, the second control circuitry configurable to: responsive to a state of the second sense terminal indicating the state change of the switching terminal, cause the second driver to provide a third current at the second drive output; and responsive to the state of the second sense terminal indicating that the switching terminal is in the particular state, cause the second driver to provide a fourth current at the second drive output, the fourth current being lower than the third current.
16. 16 . The circuit of claim 15 , further comprising a capacitor coupled between the first and second sense terminals.
17. 17 . The circuit of claim 16 , wherein the capacitor is configurable to provide a current signal responsive to a first voltage at the first sense terminal and a second voltage at the second sense terminals.
18. 18 . The circuit of claim 16 , wherein the first and second control circuitries are configurable to set a slew rate at the switching terminal responsive to a direction of a current signal into or out of the switching terminal.
19. 19 . The circuit of claim 16 , wherein the first and second control circuitries are further configurable to set a slew rate at the switching terminal responsive to whether the respective first and second transistors are turning on or off and whether a voltage at the switching terminal is rising or falling.
20. 20 . The circuit of claim 16 , wherein the capacitor and at least one of the first transistor or the second transistor are on an integrated circuit die.

Description

TECHNICAL FIELD This description relates to slew-rate control for power stages. BACKGROUND Power converters are used in variety of applications to supply electrical power. As an example, switching regulators include an arrangement of switches, such as power transistors, configured to convert electrical power from one form to another and provide a regulated voltage at an output terminal. The switching regulator is designed to maintain the regulated output voltage over a range of operating conditions, including at startup as well as under changing load conditions. Some applications specify maximum or minimum slew rates to control the speed of signal transitions for ensuring operation within expected operating parameters. Accordingly, circuits can implement slew rate control to reduce switching losses and to satisfy slew rate limits for a given application. SUMMARY One described example circuit includes high-side slew control circuitry having a high-side sense input and a high-side control output. A high-side driver has a high-side drive input and a high-side drive output. The high-side drive input is coupled to the high-side control output. A high-side transistor has a high-side control input and a high-side output. The high-side control input coupled to the high-side drive output. Low-side slew control circuitry has a low-side sense input and a low-side control output. A low-side driver has a low-side drive input and a low-side drive output. The low-side drive input is coupled to the low-side control output. A low-side transistor has a low-side control input, a ground input and a low-side output. The low-side control input is coupled to the low-side drive output, and the low-side output is coupled to the high-side output. A capacitor is coupled between the high-side sense input and the low-side sense input. Another example circuit includes a half-bridge circuit, high-side slew control circuitry, low-side slew control circuitry, high-side driver and a low-side driver. The half-bridge circuit is configured to provide a switching voltage at a respective switching output responsive to respective high-side and low-side drive signals. The high-side slew control circuitry is configured to provide a high-side slew-compensated control signal responsive to a high-side enable signal and a slew current signal representative of a slew rate at the switching output. The high-side driver is configured to provide the high-side drive signal responsive to the high-side slew-compensated control signal. The low-side slew control circuitry is configured to provide a low-side slew-compensated drive signal responsive to a low-side enable signal and the slew current signal. The low-side driver is configured to provide the low-side drive signal responsive to the low-side slew-compensated control signal. A capacitor is coupled between the high-side and low-side slew control circuitry, and the capacitor configured to convert the slew rate to the slew current signal. Another described example includes a system. A bridge circuit has a high-side control input, a low-side control input and a switching output. An inductor is coupled between the switching output and an output terminal. High-side slew control circuitry has a high-side sense input and a high-side control output. A high-side driver has a high-side drive input and a high-side drive output. The high-side drive input is coupled to the high-side control output, and the high-side drive output is coupled to the high-side control input. Low-side slew control circuitry has a low-side sense input and a low-side control output. A low-side driver has a low-side drive input and a low-side drive output. The low-side drive input is coupled to the low-side control output, and the low-side drive output is coupled to the low-side control input. A capacitor coupled between the high-side sense input and the low-side sense input. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of an example power converter circuit. FIG. 2 illustrates an example power converter circuit. FIGS. 3, 4, 5, 6, 7, 8, 9 and 10 are signal diagrams showing examples of signals in the circuits of FIGS. 1 and 2 for different switching transitions. FIG. 11 is a simplified top view of an example capacitor. FIG. 12 is a cross-sectional view of an example capacitor formed in an IC die. FIG. 13 is a cross-sectional view of another example capacitor formed in an IC die. FIG. 14 is a top view of part of an integrated circuit die showing an example layout for components of a power circuit. FIG. 15 is a flow diagram showing an example method for implementing slew control for a first low-side switching condition. FIG. 16 is a flow diagram showing an example method for implementing slew control for a second low-side switching condition. FIG. 17 is a flow diagram showing an example method for implementing slew control for a first high-side switching condition. FIG. 18 is a flow diagram showing an example method for implementing