US-12627229-B2 - Voltage booster including circuitry to reduce overvoltage stress on discharge protection device

Abstract

An apparatus including: a boost voltage generator configured to generate a boost voltage at an output; a first field effect transistor (FET) including a drain/source terminal coupled to the output of the boost voltage generator; a discharging circuit coupled to a source/drain terminal of the first FET, wherein the discharging circuit is configured to discharge the output of the boost voltage generator via the first FET in response to an asserted discharging signal; and a gate voltage boost circuit configured to generate a gate voltage for a gate of the first FET, wherein the gate voltage boost circuit is configured to boost the gate voltage in response to the asserted discharging signal. Another implementation may include a current injection circuit configured to generate and inject a current into the discharging circuit in lieu of or in addition to the gate voltage boost circuit.

Inventors

• Xiaopeng ZHONG
• Dinesh Jagannath Alladi

Assignees

• QUALCOMM INCORPORATED

Dates

Publication Date

20260512

Application Date

20221213

Claims (20)

1. 1 . An apparatus, comprising: a boost voltage generator configured to generate a boost voltage at an output; a first field effect transistor (FET) including a drain/source terminal coupled to the output of the boost voltage generator; a discharging circuit coupled to a source/drain terminal of the first FET, wherein the discharging circuit is configured to discharge the output of the boost voltage generator via the first FET in response to a discharging signal becoming asserted; and a gate voltage boost circuit configured to generate a gate voltage for a gate of the first FET, wherein the gate voltage boost circuit is configured to boost the gate voltage in response to the asserted discharging signal.
2. 2 . The apparatus of claim 1 , wherein the gate voltage boost circuit comprises a capacitor including a first terminal coupled to the gate of the first FET and a second terminal configured to receive the discharging signal.
3. 3 . The apparatus of claim 2 , wherein the discharging circuit comprises a second FET including a drain/source terminal coupled to the source/drain terminal of the first FET, a source/drain terminal coupled to a lower voltage rail, and a gate configured to receive the discharging signal.
4. 4 . The apparatus of claim 3 , wherein the discharging circuit further comprises a third FET including a source/drain terminal coupled to an upper voltage rail, a gate configured to receive the discharging signal, and a drain/source terminal coupled to the drain/source terminal of the second FET.
5. 5 . The apparatus of claim 2 , wherein the gate voltage boost circuit further comprises a resistor coupled between an upper voltage rail and the gate of the first FET.
6. 6 . The apparatus of claim 5 , wherein the gate voltage boost circuit further comprises a fourth FET including a source/drain terminal coupled to the upper voltage rail, a gate coupled to the output of the boost voltage generator, and a drain/source terminal coupled to the gate of the first FET.
7. 7 . The apparatus of claim 1 , wherein the gate voltage boost circuit is further configured to generate the gate voltage at a non-boosted level when the discharging signal is deasserted.
8. 8 . The apparatus of claim 7 , wherein the gate voltage boost circuit includes a resistor coupled between an upper voltage rail and the gate of the first FET, wherein the non-boosted level is substantially at a voltage at the upper voltage rail.
9. 9 . The apparatus of claim 1 , wherein the gate voltage boost circuit is configured to control a peak of the boosted gate voltage based on the boost voltage.
10. 10 . The apparatus of claim 9 , wherein the boosted gate voltage includes a pulse, and wherein the gate voltage boost circuit is configured to control a width of the pulse based on the boost voltage.
11. 11 . The apparatus of claim 9 , wherein the gate voltage boost circuit comprises: a capacitor including a first terminal configured to receive the discharging signal, and a second terminal coupled to the gate of the first FET; and a second FET including a source/drain terminal coupled to an upper voltage rail, a gate coupled to the output of the boost voltage generator, and a drain/source terminal coupled to the gate of the first FET.
12. 12 . The apparatus of claim 1 , further comprising a current injection circuit configured to inject a current into the discharging circuit based on a drain-to-source voltage of the first FET.
13. 13 . The apparatus of claim 12 , wherein the current injection circuit comprises a second FET including a drain/source terminal coupled to an upper voltage rail, a gate coupled to the drain/source terminal of the first FET, and a source/drain terminal coupled to the source/drain terminal of the first FET.
14. 14 . The apparatus of claim 1 , wherein the boost voltage generator comprises a bootstrapped switch voltage booster.
15. 15 . The apparatus of claim 1 , wherein the boost voltage generator comprises a charge pump voltage booster.
16. 16 . A method of reducing a boost voltage at an output of a boost voltage generator, comprising: discharging the output of the boost voltage generator via a first field effect transistor (FET) in response to a discharge signal becoming asserted; and boosting a gate voltage applied to a gate of the first FET in response to the asserted discharging signal, wherein boosting the gate voltage comprises routing the asserted discharging signal to the gate of the first FET by way of a capacitor.
17. 17 . The method of claim 16 , wherein a resistor is coupled between an upper voltage rail and the gate of the first FET, and wherein the boosted gate voltage is higher than a voltage at the upper voltage rail.
18. 18 . The method of claim 16 , further comprising controlling a peak of the boosted gate voltage.
19. 19 . The method of claim 16 , wherein the boosted gate voltage comprises a pulse, and further comprising controlling a width of the pulse.
20. 20 . The method of claim 16 , further comprising: discharging the output of the boost voltage generator via a second FET in response to the asserted discharging signal; generating an injection current; and combining the injection current with a drain-to-source current of the first FET to form a discharging current through the second FET.

Description

FIELD Aspects of the present disclosure relate generally to integrated circuits (ICs) including voltage boosters, and in particular, to a voltage booster including circuitry to reducing overvoltage stress on discharge protection device. BACKGROUND An integrated circuit (IC) may include a voltage booster to generate a boost voltage above an input voltage, such as a supply voltage on a voltage rail Vdd used by the voltage booster. For example, if the supply voltage is 0.9 Volt (V), a voltage booster may generate a boost voltage to be somewhere between 0.9V and 1.8V. To keep devices, such as field effect transistors (FETs), small for processing speed and IC footprint considerations, often the devices are implemented to have a maximum voltage rating above the supply voltage Vdd by a tolerance margin (e.g., 1.2V, where 0.9V is Vdd, and 0.3V is the tolerance margin). A boost voltage twice as high as the supply voltage Vdd may be above the voltage rating of such devices. Thus, it is of interest to protect such devices from overvoltage stress due to the boost voltage. SUMMARY The following presents a simplified summary of one or more implementations in order to provide a basic understanding of such implementations. This summary is not an extensive overview of all contemplated implementations, and is intended to neither identify key or critical elements of all implementations nor delineate the scope of any or all implementations. Its sole purpose is to present some concepts of one or more implementations in a simplified form as a prelude to the more detailed description that is presented later. An aspect of the disclosure relates to an apparatus. The apparatus includes a boost voltage generator configured to generate a boost voltage at an output; a first field effect transistor (FET) including a drain/source terminal coupled to the output of the boost voltage generator; a discharging circuit coupled to a source/drain terminal of the first FET, wherein the discharging circuit is configured to discharge the output of the boost voltage generator via the first FET in response to a discharging signal becoming asserted; and a gate voltage boost circuit configured to generate a gate voltage for a gate of the first FET, wherein the gate voltage boost circuit is configured to boost the gate voltage in response to the asserted discharging signal. Another aspect of the disclosure relates to a method of reducing a boost voltage at an output of a boost voltage generator. The method includes discharging the output of the boost voltage generator via a first field effect transistor (FET) in response to a discharge signal becoming asserted; and boosting a gate voltage applied to a gate of the first FET in response to the asserted discharging signal. Another aspect of the disclosure relates to an apparatus, comprising: a boost voltage generator configured to generate a boost voltage at an output; a first field effect transistor (FET) including a drain/source terminal coupled to the output of the boost voltage generator; a discharging circuit coupled to a source/drain terminal of the first FET, wherein the discharging circuit is configured to discharge the output of the boost voltage generator via the first FET in response to a discharging signal becoming asserted; and a current injection circuit configured to generate and inject a current into the discharging circuit. Another aspect of the disclosure relates to a method of reducing a boost voltage at an output of a boost voltage generator. The method includes discharging the output of the boost voltage generator via a first field effect transistor (FET) and a second FET in response to an asserted discharging signal applied to a gate of the second FET; generating an injection current; and combining the injection current with a drain-to-source current of the first FET to form a discharging current through the second FET. Another aspect of the disclosure relates to a wireless communication device. The wireless communication device includes: at least one antenna; a transceiver coupled to the at least one antenna, wherein the transceiver includes: a voltage booster, including: a boost voltage generator configured to generate a boost voltage at an output, a first field effect transistor (FET) including a drain/source terminal coupled to the output of the boost voltage generator, a discharging circuit coupled to a source/drain terminal of the first FET, wherein the discharging circuit is configured to discharge the output of the boost voltage generator via the first FET in response to a discharging signal becoming asserted, and a gate voltage boost circuit configured to generate a gate voltage for a gate of the first FET, wherein the gate voltage boost circuit is configured to generate the gate voltage at a boosted level in response to the asserted discharging signal; and an analog-to-digital converter (ADC) configured to use the boost voltage; and an integrated circuit (IC) including one o