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US-12627262-B2 - Generation and synchronization of pulse-width modulated (PWM) waveforms for radio-frequency (RF) applications

US12627262B2US 12627262 B2US12627262 B2US 12627262B2US-12627262-B2

Abstract

Described are concepts, systems, circuits and techniques directed toward methods and apparatus for generating one or more pulse width modulated (PWM) waveforms with the ability to dynamically control pulse width and phase with respect to a reference signal.

Inventors

  • Alexander Sergeev Jurkov
  • David J. Perreault

Assignees

  • MASSACHUSETTS INSTITUTE OF TECHNOLOGY

Dates

Publication Date
20260512
Application Date
20240216

Claims (15)

  1. 1 . A method for generating a pulse width modulated (PWM) output signal at an output of a PWM generator, the method comprising: (a) receiving a reference signal at an input of a first phase-locked loop (PLL); (b) receiving a time-delayed signal at a feedback input of the first PLL; (c) providing a signal from an output of the first PLL to a first input of a waveform combiner and to an input of a second, different PLL; (d) providing a signal from an output of the second PLL to a second input of the waveform combiner; and (e) combing, in the waveform combiner, an output signal from the first PLL and the second PLL to generate a PWM output signal.
  2. 2 . The method of claim 1 wherein: the first PLL provides a phase-shifted output signal at the output thereof; and providing the signal provided from the output of the first PLL to the input of the second, different PLL comprises providing the phase-shifted signal from the output of the first PLL to the input of the second, different PLL.
  3. 3 . The method of claim 2 wherein the phase-shifted output signal provided from the output of the first PLL to the input of the second, different PLL serves as a reference signal of the second PLL.
  4. 4 . The method of claim 1 further comprising coupling the PWM output signal from the output of the waveform combiner to an output of the PWM generator.
  5. 5 . The method of claim 1 further comprising: coupling a signal from the output of the first PLL to an input of a time-delay circuit; and coupling a signal from the output of the time-delay circuit to the input of the first PLL such that the feedback input of the first PLL receives the time-delayed signal.
  6. 6 . A method comprising: (a) receiving a reference signal at inputs of a plurality of first phase-locked loops (PLL), each of the plurality of first PLLs being in a corresponding one of a plurality of pulse width modulated (PWM) generators; (b) receiving respective ones of a plurality of time-delayed signals at respective ones of feedback inputs of the plurality of first PLLs; (c) providing a signal from an output of each of the first PLLs to a first input of a respective one of a plurality of waveform combiners, each of the plurality of waveform combiners being in a corresponding one of the plurality of PWM generators; (d) providing a signal from an output of each of the first PLLs to an input of a respective of a plurality of second PLLs, each of the plurality of second PLLs being in a corresponding one of the plurality of PWM generators; (e) providing a signal from an output of each of the plurality of second PLLs to a second input of the respective ones of the plurality of waveform combiners; and (f) combing, in the respective ones of the plurality of waveform combiners, output signals from the respective first PLLs and the second PLLs to generate a PWM signal at an output of each of the plurality of PWM generators.
  7. 7 . The method of claim 6 wherein: each of the plurality of first PLLs provides a phase-shifted output signal at the output thereof; and providing the signal provided from respective outputs of the plurality of first PLLs to the respective inputs of the second, different plurality of PLLs comprises providing the phase-shifted signal from the respective output of the plurality of first PLLs to the input of respective ones of the plurality of second, different PLLs.
  8. 8 . The method of claim 7 wherein the phase-shifted output signal provided from the outputs of the plurality of first PLLs to the inputs of respective ones of the plurality of second, different PLLs serves as a reference signal of the plurality of second PLL.
  9. 9 . The method of claim 6 further comprising: coupling a signal from the outputs of respective ones the plurality of first PLLs to a respective input of a plurality of time-delay circuits, each of the plurality of time-delay circuits being in a respective one of the plurality of pulse width modulated (PWM) generators; and coupling a signal from the outputs of the plurality of time-delay circuits to respective inputs of the plurality of first PLLs such that the feedback inputs of the plurality of first PLLs receives the time-delayed signals.
  10. 10 . A pulse width modulation (PWM) system comprising: a plurality of PWM generators having an input configured to be coupled to a reference signal source and an output and comprising; a first phase lock loop (PLL) and a second PLL coupled in a cascade configuration such that the first PLL is configured to receive a reference signal at an input thereof and an output of the first PLL is coupled to an input of the second PLL such that a phase-shifted output signal from the first PLL serves as a reference signal of the second PLL; a time delay circuit coupled to a feedback input of the first PLL; and a waveform combiner having a first input, a second input and an output with the first input of the waveform combiner coupled to the output of the first PLL, the second input of the waveform combiner coupled to the output of the second PLL and the output of the waveform combiner coupled to an output of the PWM generator, the waveform combiner responsive to phase-shifted signals provided to the first and second inputs thereof by the first and second PLLs to provide a PWM output signal Q at the output of the PWM generator.
  11. 11 . The pulse width modulation (PWM) system of claim 10 wherein an output of the first PLL is coupled through the time delay circuit to the feedback input of the first PLL.
  12. 12 . The pulse width modulation (PWM) system of claim 10 further comprising a controller coupled to respective ones of first and second PLLs and configured to provide phase-shift parameter values to the respective ones of the first and second PLLs.
  13. 13 . The pulse width modulation (PWM) system of claim 10 further comprising a reference signal source configured to provide a reference signal to the first input of the first PLL.
  14. 14 . The pulse width modulation (PWM) system of claim 10 wherein the plurality of PWM generators are configured to receive the same reference signal.
  15. 15 . The pulse width modulation (PWM) system of claim 10 wherein two of the plurality of PWM generators are configured to receive the same reference signal.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application is a continuation of U.S. application Ser. No. 17/703,230 filed Mar. 24, 2022 which is a continuation of U.S. application Ser. No. 16/932,327 filed Jul. 17, 2020, now U.S. Pat. No. 11,316,477 which is a divisional of U.S. application Ser. No. 16/126,553 filed Sep. 10, 2018, now U.S. Pat. No. 10,790,784 which is a continuation-in-part (CIP) of U.S. application Ser. No. 15/918,410 filed Mar. 12, 2018 (now abandoned) which is a continuation of U.S. application Ser. No. 14/975,742 filed on Dec. 19, 2015, now U.S. Pat. No. 9,923,518 B2 which is a continuation of U.S. application Ser. No. 14/974,563, filed on Dec. 18, 2015, now U.S. Pat. No. 9,755,576 which claims the benefit under 35 U.S.C. § 119(e) of U.S. Provisional Application No. 62/094,144, filed on Dec. 19, 2014. Application Ser. No. 14/975,742 filed on Dec. 19, 2015, now U.S. Pat. No. 9,923,518 B2 also claims the benefit under 35 U.S.C. § 119(e) of U.S. Provisional Application No. 62/094,144, filed on Dec. 19, 2014. Each of the above applications are hereby incorporated herein by reference in their entireties. STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT Not Applicable. BACKGROUND As is known in the art, impedance matching networks are commonly used for maximizing power transfer within many radio frequency (RF) and microwave systems. For example, in RF transmitters, impedance matching networks might be used to provide an impedance match from an output impedance of an RF power amplifier (PA) to an impedance of an RF load (e.g., an antenna). Such impedance matching increases the transmitted power, reduces power loss and reduces or eliminates the need for additional circuit elements (e.g., isolators, etc.). One class of impedance matching networks is referred to as tunable impedance matching networks (TMNs), sometimes called automatic antenna tuning units. Conventional TMNs might be implemented as single-element or lumped-element reactive networks where at least one of the reactive elements are variable (e.g., tunable) components such that the impedance of the variable components at a particular frequency, or over a range of frequencies, can be modified. The reactive elements within a TMN might be arranged in circuit topologies such as a ladder-network, an L-network, a T-network, or a Pi-network. Conventional TMNs can be classified as either analog (continuously adjustable) or digital (adjustable among a set of discrete values). Analog TMNs utilize variable reactance elements having reactance values (at some frequency or over a range of frequencies) that can be tuned in a continuous manner by adjusting bias conditions. Digital TMNs implement the variable reactive elements as digitally switched arrays of static reactance elements. This approach allows adjustment of the impedance of the reactance values in finite and discrete steps. Analog TMNs are often implemented using varactor diodes (or varactor diode circuits) or micro-electromechanical systems (MEMS) varactors. Although analog TMNs allow fast and accurate impedance matching over a wide range of impedances, relatively high bias voltages are required to operate at high power levels. Digital TMNs are often implemented using CMOS switches, MEMS switches, PIN diodes or discrete power transistors. Although MEMS switches have low on-state resistance and can operate up to tens of GHz with low power consumption, MEMS switches require large control voltages. PIN diode and CMOS switch-based digital TMNs exhibit low-to-moderate on-state resistance and, thus, can handle high power levels at the expense of some resistive power loss. PIN diode and CMOS switch-based digital TMNs are favorable for on-die integration, for example for Software Defined Radio (SDR) integrated circuits (ICs) and other on-chip TMNs. Digital TMNs, however, exhibit limited tuning resolution, and hence, limited accuracy with which impedance matching can be achieved. In some high power applications where accurate impedance matching is required over a very wide impedance range, such as RF plasma drivers, the use of digital TMNs can be impractical due to the large number of digital switches needed to achieve the required fine-tuning resolution. SUMMARY This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key or essential features or combinations of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter. In general overview, the concepts, systems and techniques described herein are directed toward methods and apparatus for generating one or more pulse width modulated (PWM) waveforms (signals) with the ability to dynamically control pulse width and phase with respect to a reference signal. The pulse width and phase of each PWM waveform (with respect to the reference signal) can be independentl