US-12627271-B2 - Amplifier circuit having reset mechanism

Abstract

The present disclosure discloses an amplifier circuit having reset mechanism. A pair of upper-half branches are electrically coupled between a first supply voltage and a pair of differential output terminals, are symmetrical and each includes at least one P-type transistor. A pair of lower-half branches are electrically coupled between the pair of differential output terminals and a second supply voltage, are symmetrical and each includes at least one N-type transistor. The P-type transistors and the N-type transistors are categorized into transistor groups that perform differential signal receiving process in turn in an interlaced manner under an interlaced input mode and perform reset signal receiving process to be turned on and be AC grounded when the differential signal receiving process is not performed such that the differential output terminals generate differential outputs.

Inventors

• Shih-Hsiung Huang

Assignees

• REALTEK SEMICONDUCTOR CORPORATION

Dates

Publication Date

20260512

Application Date

20230825

Priority Date

20220830

Claims (11)

1. 1 . An amplifier circuit having reset mechanism, comprising: a pair of upper-half branches electrically coupled between a first supply voltage and a pair of differential output terminals, wherein the pair of upper-half branches are symmetrical and each includes at least one P-type transistor, wherein the pair of upper-half branches are symmetrical and each comprises at least one P-type transistor; and a pair of lower-half branches electrically coupled between the pair of differential output terminals and a second supply voltage, wherein the lower-half branches are symmetrical and each comprises at least one N-type transistor; wherein the P-type transistors comprised by the upper-half branches and the N-type transistors comprised by the lower-half branches are categorized into a plurality of transistor groups such that the transistor groups in turn perform a differential signal receiving process in an interlaced manner under an interlaced input mode, and the transistor groups perform a reset signal receiving process when the differential signal receiving process is not performed to be turned on and be AC grounded such that the differential output terminals generate differential outputs; wherein each of the transistor groups includes M pairs of transistors each having a symmetrical input/output characteristic relative to the differential output terminals, M being a positive integer larger than or equal to 1.
2. 2 . The amplifier circuit of claim 1 , wherein each of the upper-half branches comprises a first P-type transistor and a second P-type transistor in turn electrically coupled between the first supply voltage and the pair of differential output terminals; wherein the first P-type transistor, the second P-type transistor, the first N-type transistor and the second N-type transistor are categorized into a first transistor group and a second transistor group.
3. 3 . The amplifier circuit of claim 2 , wherein the first P-type transistor comprised by each of the upper-half branches and the second N-type transistor comprised by each of the lower-half branches are categorized into the first transistor group, and the second P-type transistor comprised by each of the upper-half branches and the first N-type transistor comprised by the lower-half branches are categorized into the second transistor group; the first transistor group, when the differential signal receiving process is performed, is configured to receive a first differential input signal by the first P-type transistor of each of the upper-half branches and the second N-type transistor of each of the lower-half branches to generate a first differential output signal at the differential output terminals; the first transistor group, when the reset signal receiving process is performed, is configured to receive a first reset signal by the first P-type transistor of each of the upper-half branches and receive a second reset signal by the second N-type transistor of each of the lower-half branches; the second transistor group, when the differential signal receiving process is performed, is configured to receive a second differential input signal by the second P-type transistor of each of the upper-half branches and the first N-type transistor of each of the lower-half branches to generate a second differential output signal at the differential output terminals; the second transistor group, when the reset signal receiving process is performed, is configured to receive a third reset signal by the second P-type transistor of each of the upper-half branches and receive a fourth reset signal by the first N-type transistor of the lower-half branches.
4. 4 . The amplifier circuit of claim 3 , wherein the amplifier circuit provides a gain applied to the first differential input signal larger than a gain applied to the second differential input signal, and provides a power supply rejection ratio (PSRR) applied to the second differential input signal larger than a power supply rejection ratio applied to the first differential input signal.
5. 5 . The amplifier circuit of claim 2 , wherein the first P-type transistor comprised by each of the upper-half branches and the first N-type transistor comprised by each of the lower-half branches are categorized into the first transistor group, and the second P-type transistor comprised by each of the upper-half branches and the second N-type transistor comprised by each of the lower-half branches are categorized into the second transistor group; the first transistor group, when the differential signal receiving process is performed, is configured to receive a first differential input signal by the first P-type transistor of each of the upper-half branches and the first N-type transistor of each of the lower-half branches to generate a first differential output signal at the differential output terminals; the first transistor group, when the reset signal receiving process is performed, is configured to receive a first reset signal by the first P-type transistor of each of the upper-half branches and receive a second reset signal by the first N-type transistor of each of the lower-half branches; the second transistor group, when the differential signal receiving process is performed, is configured to receive a second differential input signal by the second P-type transistor of each of the upper-half branches and the second N-type transistor of each of the lower-half branches to generate a second differential output signal at the differential output terminals; the second transistor group, when the reset signal receiving process is performed, is configured to receive a third reset signal by the second P-type transistor of each of the upper-half branches and receive a fourth reset signal by the second N-type transistor of the lower-half branches.
6. 6 . The amplifier circuit of claim 5 , wherein the amplifier circuit provides a first gain applied to the first differential input signal and a second gain applied to the second differential input signal, in which a difference value between the first gain and the second gain is smaller than a predetermined value, and the amplifier circuit provides a power supply rejection ratio applied to the second differential input signal larger than a power supply rejection ratio applied to the first differential input signal.
7. 7 . The amplifier circuit of claim 2 , further comprising: two groups of input switches configured to be enabled according to an input enabling section of each of two input control signals to respectively control the first transistor group and the second transistor group to perform the differential signal receiving process to receive differential signal inputs; and two groups of reset switches configured to be enabled according to a reset enabling section of each of two reset control signals to respectively control the first transistor group and the second transistor group to perform the reset signal receiving process to receive reset signal inputs; wherein a time difference between two neighboring input enabling sections of each of the two input control signals is smaller than a predetermined value.
8. 8 . The amplifier circuit of claim 1 , wherein each of the upper-half branches comprises a P-type transistor and each of the lower-half branches comprises an N-type transistor; the P-type transistor of each of the upper-half branches is categorized into a first transistor group and the N-type transistor of each of the lower-half branches is categorized into a second transistor group; the first transistor group and the second transistor group are configured to operate in the interlaced input mode and a simultaneous input mode, so as to receive a differential input signal in different times in the interlaced input mode to generate a differential output signal at the differential output terminals, and receive the differential input signal simultaneously in the simultaneous input mode to generate the differential output signal at the differential output terminals and simultaneously stop to receive the differential input signal.
9. 9 . The amplifier circuit of claim 8 , further comprising: two groups of input switches configured to be enabled according to an input enabling section of each of two input control signals to respectively control the first transistor group and the second transistor group to perform the differential signal receiving process to receive differential signal inputs; and two groups of reset switches configured to be enabled according to a reset enabling section of each of two reset control signals to respectively control the first transistor group and the second transistor group to perform the reset signal receiving process to receive reset signal inputs; wherein a time difference between two neighboring input enabling sections of each of the two input control signals is smaller than a predetermined value.
10. 10 . The amplifier circuit of claim 8 , wherein in the interlaced input mode, either the first transistor group receives the differential input signal first and the second transistor group receives the differential input signal subsequently, or the second transistor group receives the differential input signal first and the first transistor group receives the differential input signal subsequently; in the simultaneous input mode, either the first transistor group and the second transistor group receives the differential input signal simultaneously and subsequently stops to receive the differential input signal simultaneously, or the first transistor group and the second transistor group stops to receive the differential input signal simultaneously and subsequently receives the differential input signal simultaneously.
11. 11 . The amplifier circuit of claim 8 , wherein the amplifier circuit provides a transconductance applied to the differential input signal in the simultaneous input mode larger than a transconductance applied to the differential input signal in the interlaced input mode.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present disclosure relates to an amplifier circuit having reset mechanism. 2. Description of Related Art Due to the development of portable electronic products and 5G technology, more and more applications of mobile communication and Internet of Things (IoT) are presented such that low power consumption becomes a major issue in the design of the electronic products. In analog circuits, amplifiers are the main source of power consumption and the rated voltage becomes lower and lower. As a result, the design of the complementary input amplifier becomes popular. However, when an interlaced input is performed by the complementary input amplifier, the current input signal at the input terminal may be affected by remained electrical charges of the previous input signal presented due to parasitic capacitors at the input terminal. An inter-symbol interference is thus generated. SUMMARY OF THE INVENTION In consideration of the problem of the prior art, an object of the present disclosure is to provide an amplifier circuit having reset mechanism. The present invention discloses an amplifier circuit having reset mechanism that includes a pair of upper-half branches and a pair of lower-half branches. The pair of upper-half branches are electrically coupled between a first supply voltage and a pair of differential output terminals, wherein the pair of upper-half branches are symmetrical and each includes at least one P-type transistor, wherein the pair of upper-half branches are symmetrical and each includes at least one P-type transistor. The pair of lower-half branches are electrically coupled between the pair of differential output terminals and a second supply voltage, wherein the lower-half branches are symmetrical and each includes at least one N-type transistor. The P-type transistors included by the upper-half branches and the N-type transistors included by the lower-half branches are categorized into a plurality of transistor groups such that the transistor groups in turn perform a differential signal receiving process in an interlaced manner under an interlaced input mode, and the transistor groups perform a reset signal receiving process when the differential signal receiving process is not performed to be turned on and be AC grounded such that the differential output terminals generate differential outputs. Each of the transistor groups includes M pairs of transistors each having a symmetrical input/output characteristic relative to the differential output terminals, M being a positive integer larger than or equal to 1. These and other objectives of the present disclosure will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiments that are illustrated in the various figures and drawings. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 illustrates a block diagram of an image processing circuit having output timing adjustment mechanism according to an embodiment of the present invention. FIG. 2 illustrates a waveform diagram of the input control signals and the reset control signals according to an embodiment of the present invention. FIG. 3A illustrates an equivalent circuit diagram of the amplifier circuit under the condition that the first transistor group performs the differential signal receiving process and the second transistor group performs the reset signal receiving process according to an embodiment of the present invention. FIG. 3B illustrates an equivalent circuit diagram of the amplifier circuit under the condition that the second transistor group performs the differential signal receiving process and the first transistor group performs the reset signal receiving process according to an embodiment of the present invention. FIG. 4 illustrates a circuit diagram of an amplifier circuit having reset mechanism according to another embodiment of the present invention. FIG. 5A illustrates an equivalent circuit diagram of the amplifier circuit under the condition that the first transistor group performs the differential signal receiving process and the second transistor group performs the reset signal receiving process according to an embodiment of the present invention. FIG. 5B illustrates an equivalent circuit diagram of the amplifier circuit under the condition that the second transistor group performs the differential signal receiving process and the first transistor group performs the reset signal receiving process according to an embodiment of the present invention. FIG. 6 illustrates a circuit diagram of an amplifier circuit having reset mechanism according to yet another embodiment of the present invention. FIG. 7 illustrates a waveform diagram of the input control signals and the reset control signals according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An aspect of the present invention is to provide an amplifie