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US-12627272-B2 - Enhanced gain of operational amplifiers through low-frequency zero positioning

US12627272B2US 12627272 B2US12627272 B2US 12627272B2US-12627272-B2

Abstract

An amplifier circuit comprises a multi-stage amplifier having a plurality of amplifiers cascaded between an input port V in and an output port V out to form a differential input stage and N subsequent gain stages, a capacitive load C L coupled to the output port V out , and a compensation network coupled to the multi-stage amplifier and configured for positioning Pole-Zero pairs of each stage of the multi-stage amplifier below a unity gain frequency ω t of the multi-stage amplifier when compensated, with Zeros positioned lower than Poles so as to increase the unity gain frequency ω t .

Inventors

  • Mahmood A. MOHAMMED
  • Gordon Roberts

Assignees

  • THE ROYAL INSTITUTION FOR THE ADVANCEMENT OF LEARNING/MCGILL UNIVERSITY

Dates

Publication Date
20260512
Application Date
20220520

Claims (18)

  1. 1 . An amplifier circuit comprising: a multi-stage amplifier having a plurality of amplifiers cascaded between an input port Vin and an output port V out to form a differential input stage and N subsequent gain stages, with multiple Pole-Zero pairs arising from the N gain stages; a capacitive load C L coupled to the output port V out ; and a compensation network coupled to the multi-stage amplifier and configured for positioning, using at least one compensation resistor in a kΩ range, the Pole-Zero pairs of each stage of the multi-stage amplifier at a frequency below a unity gain frequency ω t of the multi-stage amplifier when compensated, with each Zero being positioned at a lower frequency than a corresponding Pole to increase the unity gain frequency ω t and increase a phase margin of the multi-stage amplifier.
  2. 2 . The amplifier circuit of claim 1 , wherein the compensation network is further configured for positioning the Pole-Zero pairs of each stage of the multi-stage amplifier above a 3 dB frequency ω P0 of the multi-stage amplifier when compensated so as to increase a load-drive capability of the multi-stage amplifier.
  3. 3 . The amplifier circuit of claim 2 , wherein the capacitive load C L is in a range of pF to μF.
  4. 4 . The amplifier circuit of claim 3 , wherein the capacitive load C L is in a nF range.
  5. 5 . The amplifier circuit of claim 1 , wherein the multi-stage amplifier is a Miller RC differential-ended two-stage operational transconductance amplifier.
  6. 6 . The amplifier circuit of claim 1 , wherein N is an integer from 2 to 8.
  7. 7 . The amplifier circuit of claim 1 , wherein each of the N subsequent gain stages is a replicated common source gain stage.
  8. 8 . The amplifier circuit of claim 1 , wherein each of the N subsequent gain stages produces a same direct current (DC) gain as remaining ones of the N subsequent gain stages.
  9. 9 . The amplifier circuit of claim 8 , wherein each of the N subsequent gain stages has a DC gain between about 20 dB and about 25 dB.
  10. 10 . The amplifier circuit of claim 1 , wherein the compensation network comprises a plurality of compensation circuits, with a compensation circuit being provided for each stage of the multi-stage amplifier, and further wherein values of the compensation circuit for a 2-stage amplifier are scaled to size the compensation circuit of higher stages.
  11. 11 . The amplifier circuit of claim 10 , wherein the compensation circuit for each stage of the multi-stage amplifier is a multi-Miller RC compensation circuit, the plurality of compensation circuits configured to create paths between inputs and outputs of all stages of the multi-stage amplifier.
  12. 12 . The amplifier circuit of claim 11 , wherein the at least one compensation comprises a plurality of compensation resistors and the multi-stage amplifier further comprises a plurality of compensation capacitors, further wherein, when a new stage is added to the multi-stage amplifier, a size of the compensation resistors of preceding stages of the multi-stage amplifier is reduced to increase a frequency of Zeros of the new stage and a size of the compensation capacitors of the preceding stages is increased to decrease a frequency of Poles of the new stage.
  13. 13 . The amplifier circuit of claim 12 , wherein each stage higher than a second stage of the multi-stage amplifier comprises a compensation capacitor sized to a minimum capacitance value identified for the 2-stage amplifier.
  14. 14 . The amplifier circuit of claim 1 , wherein the multi-stage amplifier comprises at least one common-mode feedback circuit configured to apply biasing voltages to outputs of the stages of the multi-stage amplifier.
  15. 15 . The amplifier circuit of claim 14 , wherein, for N≤3, the at least one common-mode feedback circuit comprises a first common-mode feedback circuit.
  16. 16 . The amplifier circuit of claim 15 , wherein, for N=2, the first common-mode feedback circuit is connected to an output of a second stage of the multi-stage amplifier.
  17. 17 . The amplifier circuit of claim 15 , wherein, for N=3, the first common-mode feedback circuit is connected to an output of a third stage of the multi-stage amplifier.
  18. 18 . The amplifier circuit of claim 15 , wherein, for N≥4, the at least one common-mode feedback circuit further comprises a second common-mode feedback circuit, the first common-mode feedback circuit connected to an output of a third stage of the multi-stage amplifier and the second common-mode feedback circuit connected to an output of each additional stage following the third stage.

Description

CROSS REFERENCE TO RELATED APPLICATIONS This patent application claims priority of U.S. provisional Application Ser. No. 63/190,961, filed on May 20, 2021, the entire contents of which are hereby incorporated by reference. TECHNICAL FIELD The present disclosure generally relates to designs for amplifier circuits. BACKGROUND OF THE ART Modern analog applications require high gain and high speed operational transconductance amplifiers (OTAs). However, advanced nanometer-scale technology nodes face challenges in meeting such requirements. While recent design efforts have been focused on proposing different techniques and topologies to overcome the limitations of such scaled-down technologies, there is room for improvements. SUMMARY In accordance with one aspect, there is provided an amplifier circuit. The circuit comprises a multi-stage amplifier having a plurality of amplifiers cascaded between an input port Vin and an output port Vout to form a differential input stage and N subsequent gain stages, a capacitive load CL coupled to the output port Vout, and a compensation network coupled to the multi-stage amplifier and configured for positioning Pole-Zero pairs of each stage of the multi-stage amplifier below a unity gain frequency ωt of the multi-stage amplifier when compensated, with Zeros positioned lower than Poles so as to increase the unity gain frequency ωt. In some embodiments, the compensation network is further configured for positioning the Pole-Zero pairs of each stage of the multi-stage amplifier above a 3 dB frequency ωP0 of the multi-stage amplifier when compensated so as to increase a load-drive capability of the multi-stage amplifier. In some embodiments, the capacitive load CL is in a range of pF to μF. In some embodiments, the capacitive load CL is in a nF range. In some embodiments, the multi-stage amplifier is a Miller RC differential-ended two-stage operational transconductance amplifier. In some embodiments, N is an integer from 2 to 8. In some embodiments, each of the N subsequent gain stages is a replicated common source gain stage. In some embodiments, each of the N subsequent gain stages produces a same direct current (DC) gain as remaining ones of the N subsequent gain stages. In some embodiments, each common source gain stage has a DC gain between about 20 dB and about 25 dB. In some embodiments, the compensation network comprises a plurality of compensation circuits, with a compensation circuit being provided for each stage of the multi-stage amplifier, and further wherein values of the compensation circuit for a 2-stage amplifier are scaled to size the compensation circuit of higher stages. In some embodiments, the compensation circuit for each stage of the multi-stage amplifier is a multi-Miller RC compensation circuit, the plurality of compensation circuits configured to create paths between inputs and outputs of all stages of the multi-stage amplifier. In some embodiments, the multi-stage amplifier comprises a plurality of compensation resistors and a plurality of compensation capacitors, further wherein, when a new stage is added to the multi-stage amplifier, a size of the compensation resistors of preceding stages of the multi-stage amplifier is reduced to increase a frequency of Zeros of the new stage and a size of the compensation capacitors of the preceding stages is increased to decrease a frequency of Poles of the new stage. In some embodiments, each stage higher than the second stage comprises a compensation capacitor sized to a minimum capacitance value identified for the 2-stage amplifier. In some embodiments, the multi-stage amplifier comprises at least one common-mode feedback circuit configured to apply biasing voltages to outputs of the stages of the multi-stage amplifier. In some embodiments, for N s 3, the at least one common-mode feedback circuit comprises a first common-mode feedback circuit connected to an output of the second stage of the multi-stage amplifier. In some embodiments, for N=2, the first common-mode feedback circuit is connected to an output of a second stage of the multi-stage amplifier. In some embodiments, for N=3, the first common-mode feedback circuit is connected to an output of a third stage of the multi-stage amplifier. In some embodiments, for N≥4, the at least one common-mode feedback circuit further comprises a second common-mode feedback circuit, the first common-mode feedback circuit connected to an output of a third stage of the multi-stage amplifier and the second common-mode feedback circuit connected to an output of each additional stage following the third stage. Features described herein may be used in various combinations, in accordance with the embodiments described herein. BRIEF DESCRIPTION OF THE FIGURES Reference is now made to the accompanying figures in which: FIGS. 1A-1B show a proposed scalable many-stage OTA design; FIGS. 2A-2B are examples of transistor level implementation of a 6-stage OTA design and 8-stage OTA