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US-12627273-B2 - Analog inverter based DC offset correction circuit

US12627273B2US 12627273 B2US12627273 B2US 12627273B2US-12627273-B2

Abstract

One aspect can provide a direct current (DC) feedback circuit. The DC feedback circuit can include a gain path, a first feedback capacitor coupled, in parallel, to the gain path, and an input resistor coupled to an input of the gain path and the first feedback capacitor. The gain path can include an input stage with a pair of transconductance amplifiers, a gain stage with one or more amplifiers, and an output stage with at least one negative feedback amplifier.

Inventors

  • Ryan Barnhill
  • Jacquelyn Mary Ingemi
  • MICHAEL JAMES MARSHALL
  • James S. Ignowski

Assignees

  • HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Dates

Publication Date
20260512
Application Date
20221028

Claims (19)

  1. 1 . A direct current (DC) feedback circuit, the circuit comprising: a gain path; a first feedback capacitor coupled, in parallel, to the gain path; and an input resistor coupled to an input of the gain path and the first feedback capacitor, the gain path, the first feedback capacitor, and the input resistor forming a first Miller circuit that amplifies a capacitance of the first feedback capacitor; wherein the gain path comprises an input stage with a pair of transconductance amplifiers, an adjustable gain stage comprising a plurality of cascaded amplifiers, and an output stage; wherein the adjustable gain stage comprises a selector switch comprising a plurality of pass/transmission gates coupled to the plurality of cascaded amplifiers in the adjustable gain stage; wherein the output stage comprises a second Miller circuit comprising a second feedback capacitor; and wherein a capacitance of the second feedback capacitor is smaller than the capacitance of the first feedback capacitor.
  2. 2 . The DC feedback circuit of claim 1 , wherein a capacitance of the first feedback capacitor is between 10 pF and 50 pF.
  3. 3 . The DC feedback circuit of claim 2 , wherein a cutoff frequency of the DC feedback circuit is between 100 KHz and 1 MHz.
  4. 4 . The DC feedback circuit of claim 1 , wherein the pair of transconductance amplifiers are inverting amplifiers, and wherein a transconductance ratio between the pair of transconductance amplifiers is between one and five.
  5. 5 . The DC feedback circuit of claim 1 , wherein the second Miller circuit is to provide stability to the DC feedback circuit, and wherein the second Miller circuit further comprises an inverting amplifier and a resistor.
  6. 6 . The DC feedback circuit of claim 5 , wherein a resistance of the resistor in the second Miller circuit is smaller than a resistance of the input resistor in the first Miller circuit.
  7. 7 . The DC feedback circuit of claim 1 , wherein the first feedback capacitor is coupled to the gain path via a switch.
  8. 8 . The DC feedback circuit of claim 1 , wherein the amplifiers in the gain stage comprise inverting amplifiers, and wherein a total number of inverting amplifiers in the circuit is determined to ensure that the circuit provides a negative DC feedback.
  9. 9 . The DC feedback circuit of claim 1 , further comprising an inverter coupled to an output of the gain path and the first feedback capacitor.
  10. 10 . The DC feedback circuit of claim 1 , wherein the input resistor is coupled to an output of a to-be-compensated circuit, and wherein an output of the gain path is coupled to an input of the to-be-compensated circuit, thereby allowing the DC-feedback circuit to provide DC-offset compensation to the to-be-compensated circuit.
  11. 11 . The DC feedback circuit of claim 10 , wherein the to-be-compensated circuit is a frontend circuit of a high-speed receiver.
  12. 12 . A high-speed receiver frontend circuit, comprising: a plurality of cascaded amplifier stages; and a DC-offset-compensation circuit coupled to one or more cascaded amplifier stages to provide DC-offset compensation; wherein the DC-offset-compensation circuit comprises: a gain path; a first feedback capacitor coupled, in parallel, to the gain path; and an input resistor coupled to an input of the gain path and the first feedback capacitor, the gain path, the first feedback capacitor, and the input resistor forming a first Miller circuit that amplifies a capacitance of the first feedback capacitor; wherein the gain path comprises an input stage with a pair of transconductance amplifiers, an adjustable gain stage comprising a plurality of cascaded amplifiers, and an output stage; wherein the adjustable gain stage comprises a selector switch comprising a plurality of pass/transmission gates coupled to the plurality of cascaded amplifiers in the adjustable gain stage; wherein the output stage comprises a second Miller circuit comprising a second feedback capacitor; and wherein a capacitance of the second feedback capacitor is smaller than the capacitance of the first feedback capacitor.
  13. 13 . The receiver frontend circuit of claim 12 , wherein a capacitance of the first feedback capacitor is between 10 pF and 50 pF.
  14. 14 . The receiver frontend circuit of claim 12 , wherein the pair of transconductance amplifiers are inverting amplifiers, and wherein a transconductance ratio between the pair of transconductance amplifiers is between one and ten.
  15. 15 . The receiver frontend circuit of claim 12 , wherein the second Miller circuit is to provide stability to the DC-offset-compensation circuit, and wherein the second Miller circuit further comprises an inverting amplifier and a resistor.
  16. 16 . The receiver frontend circuit of claim 15 , wherein a resistance of the resistor in the second Miller circuit is smaller than a resistance of the input resistor in the first Miller circuit.
  17. 17 . The receiver frontend circuit of claim 12 , wherein the first feedback capacitor is coupled to the gain path via a switch.
  18. 18 . The receiver frontend circuit of claim 12 , wherein the amplifiers in the gain stage comprise one or more inverting amplifiers, and wherein a total number of inverting amplifiers in the circuit is determined to ensure that the DC-offset-compensation circuit provides a negative DC feedback to the coupled one or more cascaded amplifier stages.
  19. 19 . The receiver frontend circuit of claim 12 , wherein the DC-offset-compensation circuit further comprises an inverter coupled to an output of the gain path and the first feedback capacitor.

Description

BACKGROUND Field This disclosure is generally related to analog circuit design. More specifically, this disclosure is related to the design of a direct current (DC)-offset-compensation circuit. BRIEF DESCRIPTION OF THE FIGURES FIG. 1 illustrates an example of the schematic of a DC-offset-compensation circuit, according to one aspect of the instant application. FIG. 2 illustrates an example of a DC-offset-compensation circuit, according to one aspect of the instant application. FIG. 3 illustrates an example of a DC-offset-compensation circuit, according to one aspect of the instant application. FIG. 4 illustrates an example of a DC-offset-compensation circuit, according to one aspect of the instant application. FIG. 5 illustrates an example of a receiver frontend implementing a DC-offset-compensation circuit, according to one aspect of the instant application. FIG. 6 presents a flowchart illustrating an example of a process for designing a DC-offset-compensation circuit, according to one aspect of the instant application. In the figures, like reference numerals refer to the same figure elements. DETAILED DESCRIPTION The following description is presented to enable any person skilled in the art to make and use the embodiments and is provided in the context of a particular application and its requirements. Various modifications to the disclosed embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the present disclosure. Thus, the scope of the present disclosure is not limited to the embodiments shown but is to be accorded the widest scope consistent with the principles and features disclosed herein. Due to random as well as systematic variation in the fabrication process (e.g., the size and property variations of the transistors), analog circuits often suffer from intrinsic offset, such as direct current (DC) offset, which can be a fixed voltage that is permanently present on the signal of interest. Without compensation, the DC offset may saturate the amplifier output stage, which can in turn reduce the amplifier dynamic range and may interfere with the amplification of the desired signal. Moreover, differential signaling is widely used in serializer/deserializer (SerDes) systems, and due to the mismatch between the devices (e.g., amplifiers) in the circuitry processing the two complimentary signals, an offset voltage will be introduced into the differential signals. Such an offset can affect the noise margin of the SerDes systems. A typical DC-offset-correction or DC-offset-compensation circuit can include a feedback path that feeds back a negative version of the DC component of the output of a to-be-compensated circuit to its input in order to cancel the DC offset at the input. For example, the feedback path can include current-mode logic (CML)-based differential amplifiers that can function as a low-pass filter such that only the DC or close-to-DC component of the output can be fed back to the input. To sufficiently compensate for the DC offset without affecting the signal of interest (e.g., signals at a higher frequency), the cutoff or corner frequency of the feedback circuit should be as close as possible to DC. If the cutoff frequency is not sufficiently low, the DC-offset-correction circuit may end up tracking the data itself (i.e., feeding the data back to the input), potentially causing bit errors. However, the implementation constraints of the high-speed circuit (e.g., the high-speed SerDes) often limit how low the cutoff frequency can be. More particularly, achieving a low cutoff frequency often requires a large capacitor, meaning that the area burden for implementing the DC-offset-compensation circuit can be large and undesirable. To reduce the area burden that comes with a large capacitor, according to some aspects of the disclosure, instead of using a large capacitor, the DC-offset-compensation circuit can use the Miller effect to increase the equivalent capacitance of a circuit with a smaller capacitor. More particularly, when a capacitor C is connected to both the input and output of an inverting voltage amplifier, due to the application of the effect of the capacitance between the input and output terminals, the input capacitance of the amplifier is increased to CM=C(1+Av), where the gain of the inverting voltage amplifier is −Av. According to the Miller effect, the larger the amplifier gain, the larger the amplification of the capacitance. To sufficiently reduce the cutoff frequency of the DC-offset-compensation circuit without a significant area burden, some aspects of the instant application provide a feedback circuit with multiple gain stages. FIG. 1 illustrates an example of the schematic of a DC-offset-compensation circuit, according to one aspect of the instant application. A DC-offset-compensation circuit 100 can include an input sta