US-12627274-B2 - Methods, systems, and apparatus for coupling power amplifier input signals

Abstract

Methods, systems, and apparatus are disclosed for coupling a power amplifier input signal. An example system a first amplifier including a signal input, a feedback input, and a differential output that includes a first output and a second output, a first resistor including a first resistor terminal and a second resistor terminal, wherein the first resistor terminal is coupled to the first output, a second resistor including a third resistor terminal and a fourth resistor terminal, wherein the third resistor terminal is coupled to the second resistor terminal at an output common mode node and the fourth resistor terminal coupled to the second output, and a second amplifier including a first input and a third output, wherein the first input is coupled to the second resistor terminal and third resistor terminal, and the third output is coupled to the feedback input of the first amplifier.

Inventors

• Rohit Chatterjee

Assignees

• TEXAS INSTRUMENTS INCORPORATED

Dates

Publication Date

20260512

Application Date

20230816

Claims (20)

1. 1 . A system comprising: a first amplifier including a signal input, a feedback input, and a differential output that includes a first output and a second output; a first resistor including a first resistor terminal and a second resistor terminal, wherein the first resistor terminal is coupled to the first output; a second resistor including a third resistor terminal and a fourth resistor terminal, wherein the third resistor terminal is coupled to the second resistor terminal at an output common mode node and the fourth resistor terminal coupled to the second output; and a second amplifier including a first input and a third output, wherein the first input is coupled to the second resistor terminal and third resistor terminal, and the third output is coupled to the feedback input of the first amplifier.
2. 2 . The system of claim 1 , wherein the feedback input is coupled to receive a correction signal from the third output, wherein the correction signal is to cause the first amplifier to adjust a common mode voltage at the output common mode node.
3. 3 . The system of claim 1 , wherein the second amplifier includes a second input and the system further comprises envelope detection circuitry to provide a dynamic bias voltage to the second input.
4. 4 . The system of claim 1 , further comprising envelope detection circuitry including: a full-wave rectifier base level detector including a second input, a third input, and a fourth output, wherein the second input and third input are coupled to receive differential first amplified signals; and a filter including a fourth input and a dynamic bias output, wherein the fourth input is coupled to the fourth output of the full-wave rectifier base level detector and the dynamic bias output is coupled to fifth input of the second amplifier.
5. 5 . The system of claim 1 , further comprising a third amplifier including a second input and a third input, wherein the second input is coupled to the first output and the third input is coupled to the second output.
6. 6 . The system of claim 1 , further comprising: envelope detection circuitry including a second input, a third input, and a dynamic bias output, wherein the dynamic bias output is coupled to a fourth input of the second amplifier; and a third amplifier including a fourth output and a fifth output, wherein the fourth output is coupled to the second input and coupled to the signal input, the fifth output is coupled to the third input and coupled to the signal input.
7. 7 . The system of claim 1 , further comprising a third amplifier including a fourth output and a fifth output, wherein the fourth output is coupled to the signal input of the first amplifier and the fifth output is coupled to the signal input.
8. 8 . The system of claim 1 , further comprising: a third amplifier; a first capacitor including a first capacitor terminal and a second capacitor terminal, wherein the first capacitor terminal is coupled to a fourth output of the third amplifier and the second capacitor terminal coupled to the signal input of the first amplifier; and a second capacitor including a third capacitor terminal and a fourth capacitor terminal, wherein the third capacitor terminal is coupled to a fifth output of the third amplifier and the fourth capacitor terminal coupled to the signal input.
9. 9 . The system of claim 1 , wherein the first amplifier is a preamplifier.
10. 10 . The system of claim 1 , wherein the second amplifier is a common mode feedback (CMFB) amplifier.
11. 11 . A circuit comprising: a first transistor including a first gate terminal, a first drain terminal, and a first source terminal; a first resistor including a first resistor terminal and a second resistor terminal, wherein the first resistor terminal is coupled to the first drain terminal; a second transistor including a second gate terminal, a second drain terminal, and a second source terminal; a second resistor including a third resistor terminal and a fourth resistor terminal, wherein the third resistor terminal is coupled to the second drain terminal and the fourth resistor terminal is coupled to the second resistor terminal at an output common mode node; a third transistor including a third gate terminal, a third drain terminal, and a third source terminal, wherein the third drain terminal is coupled to the first resistor terminal and to the first drain terminal; and a fourth transistor including a fourth gate terminal, a fourth drain terminal, and a fourth source terminal, wherein the fourth drain terminal is coupled to the third resistor terminal and to the second drain terminal, and the fourth gate terminal is coupled to the third gate terminal.
12. 12 . The circuit of claim 11 , further comprising: a first capacitor coupled to the first gate terminal; and a second capacitor coupled to the second gate terminal.
13. 13 . The circuit of claim 11 , further comprising: a third resistor coupled the first gate terminal; and a fourth resistor coupled the second gate terminal.
14. 14 . The circuit of claim 11 , further comprising: a current source; a fifth transistor including a fifth gate terminal, a fifth drain terminal, and a fifth source terminal, wherein the fifth drain terminal is coupled to the current source and to the fifth gate terminal; and a third resistor including a fifth resistor terminal and a sixth resistor terminal, wherein the fifth resistor terminal is coupled to the fifth gate terminal and the sixth resistor terminal coupled to the first gate terminal.
15. 15 . The circuit of claim 11 , wherein the first transistor and the second transistor are n-channel metal-oxide semiconductor (NMOS) transistors.
16. 16 . The circuit of claim 11 , wherein the third transistor and the fourth transistor are p-channel metal-oxide semiconductor (PMOS) transistors.
17. 17 . The circuit of claim 11 , wherein the third gate terminal and the fourth gate terminal are coupled to receive a correction signal, wherein the correction signal is to cause the first transistor and the second transistor to adjust a common mode voltage at the output common mode node.
18. 18 . The circuit of claim 17 , wherein the first resistor and the second resistor are averaging resistors, wherein the averaging resistors are to generate the common mode voltage of a first voltage at the first drain terminal and a second voltage at the second drain terminal.
19. 19 . An apparatus comprising: signal processing circuitry including a first data output and a second data output; pre-amplifier circuitry including: a first amplifier including a first input, a second input, a first output, and a second output, wherein the first input is coupled to receive the first data output and the second input is coupled to receive the second data output; a second amplifier including a third input, a fourth input, a feedback input, a differential output that includes a third output and a fourth output, wherein the third input ( 234 a ) is coupled to the first output and the fourth input is coupled to the second output; a third amplifier including a fifth input, a sixth input, and a feedback output, the feedback output coupled to the feedback input; and averaging resistors coupled to the third and fourth outputs and coupled to the fifth input; a power amplifier including a seventh input and an eighth input, the seventh input coupled to the third output and the eighth input coupled to the fourth output; and an antenna coupled to an output of the power amplifier.
20. 20 . The apparatus of claim 19 , further including a mixer to: receive the first data output and the second data output; generate a first modulated signal based on the first data output and a second modulated signal based on the second data output; output the first modulated signal to the first input; and output the second modulated signal to the second input.

Description

FIELD OF THE DISCLOSURE This disclosure relates generally to power amplifier input signals and, more particularly, to methods, systems, and apparatus for coupling power amplifier input signals. BACKGROUND Some electronic devices include one or more transceivers to communicate with other devices using radio frequency (RF) signals. Such transceivers include RF power amplifiers to convert low-power RF signals to higher power signals. The higher power signals drive an antenna of the transceiver to transmit data, included in the low-power RF signal to other devices. Some power amplifiers are coupled to other stages of a transceiver, such as an input stage and an output stage. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of an example transmitter to transmit an information signal. FIG. 2 is a schematic illustration of example pre-amplifier circuitry of FIG. 1 including a common path for modulated signals and bias voltage. FIG. 3 is a schematic illustration of an example second pre-power amplifier of the pre-amplifier circuitry of FIG. 2. FIG. 4 is a schematic illustration of example envelope detection circuitry of FIG. 2 to track the envelope of an output of an example first pre-power amplifier of the pre-amplifier circuitry of FIG. 2 and generate a dynamic bias voltage based on the envelope. FIG. 5 is a block diagram of an example processing platform including programmable circuitry structured to implement the signal processing circuitry 102 of the transmitter of FIG. 1. In general, the same reference numbers will be used throughout the drawing(s) and accompanying written description to refer to the same or like parts. The figures are not necessarily to scale. Instead, the thickness of the layers or regions may be enlarged in the drawings. Although the figures show layers and regions with clean lines and boundaries, some or all of these lines and/or boundaries may be idealized. In reality, the boundaries and/or lines may be unobservable, blended, and/or irregular. As used herein, connection references (e.g., attached, coupled, connected, and joined) may include intermediate members between the elements referenced by the connection reference and/or relative movement between those elements unless otherwise indicated. As such, connection references do not necessarily infer that two elements are directly connected and/or in fixed relation to each other. Unless specifically stated otherwise, descriptors such as “first,” “second,” “third,” etc., are used herein without imputing or otherwise indicating any meaning of priority, physical order, arrangement in a list, and/or ordering in any way, but are merely used as labels and/or arbitrary names to distinguish elements for ease of understanding the disclosed examples. In some examples, the descriptor “first” may be used to refer to an element in the detailed description, while the same element may be referred to in a claim with a different descriptor such as “second” or “third.” In such instances, it should be understood that such descriptors are used merely for identifying those elements distinctly within the context of the discussion (e.g., within a claim) in which the elements might, for example, otherwise share a same name. As used herein, “approximately” and “about” modify their subjects/values to recognize the potential presence of variations that occur in real world applications. For example, “approximately” and “about” may modify dimensions that may not be exact due to manufacturing tolerances and/or other real world imperfections as will be understood by persons of ordinary skill in the art. For example, “approximately” and “about” may indicate such dimensions may be within a tolerance range of +/−10% unless otherwise specified in the below description. As used herein, the phrase “in communication,” including variations thereof, encompasses direct communication and/or indirect communication through one or more intermediary components, and does not require direct physical (e.g., wired) communication and/or constant communication, but rather additionally includes selective communication at periodic intervals, scheduled intervals, aperiodic intervals, and/or one-time events. As used herein integrated circuit/circuitry is defined as one or more semiconductor packages containing one or more circuit elements such as transistors, capacitors, inductors, resistors, current paths, diodes, etc. For example an integrated circuit may be implemented as one or more of an ASIC, an FPGA, a chip, a microchip, programmable circuitry, a semiconductor substrate coupling multiple circuit elements, a system on chip (SoC), etc. DETAILED DESCRIPTION The demand for smaller, lighter, and more portable electronic devices such as smartphones, laptops, wearables, and IoT (Internet of Things) devices is on the rise. Reduced die sizes enable manufacturers to pack more functionality into compact form factors on an integrated circuit (IC), making it easier for consumers to carry