US-12627276-B2 - Power regulation circuit and method for chip

Abstract

Provided are a power regulation circuit and method for a chip, and a power supply circuit for a circuit. The power regulation circuit includes an LC circuit and an LC correction circuit. One terminal of the LC circuit is electrically connected to a positive pole of a chip and a positive electrode of a power supply. The other terminal of the LC circuit is electrically connected to a negative pole of the chip and a negative pole of the power supply. The LC correction circuit is electrically connected to the chip and the LC circuit, and is used to regulate a working parameter of the LC circuit according to the current working mode of the chip.

Inventors

• RANGTIAN LU
• Xianhong Wang
• PENGFANG LV
• CHANGQING WEN
• AIMEI LIANG

Assignees

• SHENZHEN PANGO MICROSYSTEMS CO., LTD.

Dates

Publication Date

20260512

Application Date

20230630

Priority Date

20210106

Claims (16)

1. 1 . A power regulation circuit for a chip, comprising: an LC circuit; an adjustable resistor connected in series with the LC circuit, wherein one terminal of a series circuit constituted by the adjustable resistor and the LC circuit is electrically connected to each of a positive pole of the chip and a positive pole of a power supply, and the other terminal of the series circuit constituted by the adjustable resistor and the LC circuit is electrically connected to each of a negative pole of the chip and a negative pole of the power supply; an LC correction circuit, wherein the LC correction circuit is electrically connected to each of the chip and the LC circuit, and is configured to adjust a working parameter of the LC circuit according a current working mode of the chip; and an impedance configuration circuit, wherein the impedance configuration circuit is electrically connected to each of the chip and the adjustable resistor, and is configured to adjust a resistance value of the adjustable resistor according to the current working mode of the chip; wherein the impedance configuration circuit is further configured to acquire a current of the chip in the current working mode and a rated voltage of the chip; and adjust the resistance value of the adjustable resistor, according to the rated voltage and the current, wherein a product of the adjusted resistance value and the current matches the rated voltage.
2. 2 . The power regulation circuit for a chip of claim 1 , wherein the LC correction circuit is configured to determine a current clock signal of the chip, according to the current working mode of the chip; and adjust the working parameter of the LC circuit according to the current clock signal of the chip.
3. 3 . The power regulation circuit for a chip of claim 2 , wherein the LC correction circuit is configured to determine a working frequency of the chip according to the current clock signal of the chip; and adjust a resonant frequency of the LC circuit according to the working frequency of the chip.
4. 4 . The power regulation circuit for a chip of claim 1 , wherein the LC circuit comprises an adjustable capacitor and an adjustable inductor connected in series with each other, one terminal of a further series circuit constituted by the adjustable capacitor and the adjustable inductor is electrically connected to one terminal of the adjustable resistor, another terminal of the adjustable resistor is electrically connected to each of the positive pole of the chip and the positive pole of the power supply, and the other terminal of the further series circuit constituted by the adjustable capacitor and the adjustable inductor is electrically connected to each of the negative pole of the chip and the negative pole of the power supply; and the LC correction circuit is electrically connected to each of the adjustable capacitor and the adjustable inductor, and is configured to adjust, according to the current working mode of the chip, an inductance value of the adjustable inductor and a capacitance value of the adjustable capacitor, to make a resonant frequency of the LC circuit match the current working mode of the chip.
5. 5 . The power regulation circuit for a chip of claim 1 , wherein the impedance configuration circuit is further is configured to determine that the product of the adjusted resistance value and the current matches the rated voltage and stop adjustment of the adjustable resistor, when it is detected that an absolute value of a difference between the rated voltage and the product of the adjusted resistance value and the current does not exceed a specified value.
6. 6 . The power regulation circuit for a chip of claim 1 , wherein the LC correction circuit is further configured to receive an enabling signal output by the chip; and control a working state of the LC correction circuit according to the enabling signal; and the impedance configuration circuit is further configured to receive the enabling signal output by the chip; and control a working state of the impedance configuration circuit according to the enabling signal.
7. 7 . A power regulation method for a chip, wherein the method is implemented by a power regulation circuit for a chip, the power regulation circuit comprises an LC circuit, an LC correction circuit, an adjustable resistor and an impedance configuration circuit, one terminal of a series circuit constituted by the adjustable resistor and the LC circuit is electrically connected to each of a positive pole of the chip and a positive pole of a power supply, and the other terminal of the series circuit constituted by the adjustable resistor and the LC circuit is electrically connected to each of a negative pole of the chip and a negative pole of the power supply, the LC correction circuit is electrically connected to each of the chip and the LC circuit, the impedance configuration circuit is electrically connected to each of the chip and the adjustable resistor, and the method comprises: acquiring, by the LC correction circuit, a current working mode of the chip; adjusting, by the LC correction circuit, a working parameter of the LC circuit according to the current working mode of the chip, acquiring a current of the chip in the current working mode and a rated voltage of the chip; and adjusting, by the impedance configuration circuit, a resistance value of the adjustable resistor, according to the rated voltage and the current, wherein a product of the adjusted resistance value and the current matches the rated voltage.
8. 8 . The power regulation method for a chip of claim 7 , wherein the adjusting a working parameter of the LC circuit according to the current working mode of the chip, comprises: determining a current clock signal of the chip, according to the current working mode of the chip; and adjusting the working parameter of the LC circuit, according to the current clock signal.
9. 9 . The power regulation method for a chip of claim 7 , wherein the adjusting a working parameter of the LC circuit according to the current working mode of the chip, comprises: determining a working frequency of the chip, according to a current clock signal of the chip; and adjusting the working parameter of the LC circuit according to the working frequency of the chip.
10. 10 . The power regulation method for a chip of claim 8 , wherein the LC circuit comprises an adjustable capacitor and an adjustable inductor connected in series with each other, the adjusting a working parameter of the LC circuit according to the current working mode, comprises: adjusting, according to the current clock signal, an inductance value of the adjustable inductor and a capacitance value of the adjustable capacitor, to adjust a resonant frequency of the LC circuit, wherein the adjusted resonant frequency matches the current clock signal.
11. 11 . The power regulation method for a chip of claim 7 , wherein the adjusting the resistance value of the adjustable resistor according to the rated voltage and the current, comprises: in response to detecting that an absolute value of a difference between the rated voltage and the product of the adjusted resistance value and the current does not exceed a specified value, determining that the product of the adjusted resistance value and the current matches the rated voltage, and stopping adjustment of the adjustable resistor.
12. 12 . The power regulation method for a chip of claim 7 , further comprising: receiving an enabling signal output by the chip; and controlling, according to the enabling signal, working states of the impedance configuration circuit and the LC correction circuit.
13. 13 . A power supply circuit for a chip, comprising: a power supply; an LC circuit; an adjustable resistor connected in series with the LC circuit, wherein one terminal of a series circuit constituted by the adjustable resistor and the LC circuit is electrically connected to each of a positive pole of the chip and a positive pole of the power supply, and the other terminal of the series circuit constituted by the adjustable resistor and the LC circuit is electrically connected to each of a negative pole of the chip and a negative pole of the power supply; an LC correction circuit, wherein the LC correction circuit is electrically connected to each of the chip and the LC circuit, and is configured to adjust a working parameter of the LC circuit according a current working mode of the chip; and an impedance configuration circuit, wherein the impedance configuration circuit is electrically connected to each of the chip and the adjustable resistor, and is configured to: acquire a current of the chip in the current working mode and a rated voltage of the chip, and adjust a resistance value of the adjustable resistor, according to the rated voltage and the current, wherein a product of the adjusted resistance value and the current matches the rated voltage.
14. 14 . The power supply circuit for a chip of claim 13 , wherein the LC circuit comprises an adjustable capacitor and an adjustable inductor connected in series with each other, one terminal of the adjustable capacitor is connected with one terminal of the adjustable inductor, the other terminal of the adjustable capacitor is electrically connected to one terminal of the adjustable resistor, another terminal of the adjustable resistor is electrically connected to each of the positive pole of the chip and the positive pole of the power supply, and the other terminal of the adjustable inductor is electrically connected to each of the negative pole of the chip and the negative pole of the power supply; and the LC correction circuit is electrically connected to each of the adjustable capacitor and the adjustable inductor, and is configured to adjust, according to the current working mode of the chip, an inductance value of the adjustable inductor and a capacitance value of the adjustable capacitor, to make a resonant frequency of the LC circuit match the current working mode of the chip.
15. 15 . The power supply circuit for a chip of claim 13 , further comprising: an on-chip decoupling capacitor, wherein a first terminal of the on-chip decoupling capacitor is electrically connected to each of the positive pole of the power supply and the positive pole of the chip, and a second terminal of on-chip decoupling capacitor is electrically connected to each of the negative pole of the power supply and the negative pole of the chip; and two parasitic inductors, wherein one of the two parasitic inductors is connected in series between an the on-chip decoupling capacitor and the positive pole of the power supply, and the other one of the two parasitic inductors is connected in series between the on-chip decoupling capacitor and the negative pole of the power supply.
16. 16 . The power supply circuit for a chip of claim 13 , wherein the impedance configuration circuit is further is configured to determine that the product of the adjusted resistance value and the current matches the rated voltage and stop adjustment of the adjustable resistor, when it is detected that an absolute value of a difference between the rated voltage and the product of the adjusted resistance value and the current does not exceed a specified value.

Description

CROSS-REFERENCE OF RELEVANT APPLICATIONS The present disclosure is a continuation of International Application PCT/CN2021/079740 filed on Mar. 9, 2021, which claims priority to a Chinese Patent Application No. 202110014731.1 filed on Jan. 6, 2021. The entire contents of these applications are incorporated herein by reference. TECHNICAL FIELD The present disclosure relates to the field of integrated circuits, and particularly relates to a power regulation circuit and method for a chip, and a power supply circuit for a chip. BACKGROUND In designing an integrated circuit, the power integrity should be considered to ensure the performance of a chip. For example, for a high-performance digital integrated circuit (IC) chip, such as a central processing unit (CPU) and a field programmable gate array (FPGA), while ensuring the power integrity of the chip during its operation, it is necessary to ensure that the power voltage of the chip is within a certain tolerance, and that a direct current error, a ripple, and a noise of the chip are all within an allowable range. However, a power circuit generally has a fixed resonant frequency; and if the working frequency of the chip changes, the resonant frequency of the power circuit cannot match the working frequency of the chip, which cannot well ensure the power integrity of the chip. SUMMARY In view of the above, the present disclosure provides a power regulation circuit and method for a chip, and a power supply circuit for a chip. In a first aspect, the embodiments of the present disclosure provide a power regulation circuit for a chip. The power regulation circuit includes an LC circuit and an LC correction circuit. One terminal of the LC circuit is electrically connected to each of a positive pole of the chip and a positive pole of a power supply, and the other terminal of the LC circuit is electrically connected to each of a negative pole of the chip and a negative pole of the power supply. The LC correction circuit is electrically connected to each of the chip and the LC circuit, and the LC correction circuit is used to adjust a working parameter of the LC circuit according to a current working mode of the chip. In a second aspect, the embodiments of the present disclosure provide a power regulation method for a chip. The method is implemented by the power regulation circuit for a chip in the first aspect, and the method includes: acquiring a current working mode of the chip; and adjusting a working parameter of the LC circuit according to the current working mode. In a third aspect, the embodiments of the present disclosure provide a power supply circuit for a chip. The power supply circuit includes a power supply, an LC circuit, and an LC correction circuit. One terminal of the LC circuit is electrically connected to each of a positive pole of the chip and a positive pole of the power supply, and the other terminal of the LC circuit is electrically connected to each of a negative pole of the chip and a negative pole of the power supply. The LC correction circuit is electrically connected to each of the chip and the LC circuit, and is configured to adjust a working parameter of the LC circuit according a current working mode of the chip. In the power regulation circuit and method for a chip and the power supply circuit for a chip as provided in the embodiments of the present disclosure, the power regulation circuit for a chip is constituted by an LC circuit and an LC correction circuit. One terminal of the LC circuit is electrically connected to each of a positive pole of the chip and a positive pole of a power supply, and the other terminal of the LC circuit is electrically connected to each of a negative pole of the chip and a negative pole of the power supply. The LC correction circuit is electrically connected to each of the chip and the LC circuit. When the power supply supplies power to the chip, the LC correction circuit can adjust a working parameter of the LC circuit according to the current working mode of the chip, to enable self-adaptation of the resonant frequency of the power supply; and even if the working frequency of the chip changes due to the change of the working mode thereof, the power integrity of the chip can be ensured. BRIEF DESCRIPTION OF THE DRAWINGS To illustrate the technical schemes in the embodiments of the present disclosure clearly, drawings used in the description of the embodiments are briefly introduced below. Apparently, the drawings in the following description are merely some embodiments of the present disclosure. For those skilled in the art, other drawings may be obtained according to these drawings without paying any creative effort. FIG. 1 illustrates a schematic circuit diagram of a power circuit for a chip in the related art. FIG. 2 illustrates a schematic circuit diagram of a power circuit for a chip according to an embodiment of the present disclosure. FIG. 3 illustrates a schematic circuit diagram of a power circuit f