US-12627283-B2 - Circuit for detecting timing violations in a digital circuit

US12627283B2US 12627283 B2US12627283 B2US 12627283B2US-12627283-B2

Abstract

The present disclosure relates to a circuit comprising: —a first timing guard circuit ( 200 ) configured to detect when a slack time of a first data signal arriving at a first synchronous device ( 202 ) falls below a first threshold (SLG DELAY); and —a second timing guard circuit ( 200 ) configured to detect when a slack time of a second data signal arriving at a second synchronous device ( 202 ) falls below a second threshold (SLG DELAY), the first and second thresholds being different from each other.

Inventors

Mathieu Louvat
François Jacquet

Assignees

DOLPHIN SEMICONDUCTOR

Dates

Publication Date: 20260512
Application Date: 20220715
Priority Date: 20210715

Claims (13)

1 . A circuit comprising: a plurality of first timing guard circuits each configured to detect when a slack time of a first data signal arriving at a first synchronous device falls below a first threshold; a second timing guard circuit configured to detect when a slack time of a second data signal arriving at a second synchronous device falls below a second threshold, the first and second thresholds being different from each other; and a timing response circuit configured to: receive status flag signals from the plurality of first timing guard circuits when the slack time of the first data signal falls below the first threshold; compare a number of flags signals generated by the plurality of first timing guard circuits with a threshold; and apply, in response to the number of flag signal exceeding the threshold, a first supply voltage or biasing voltage adjustment and/or a first frequency reduction to a clock signal of the circuit.
2 . The circuit of claim 1 , wherein: the first data signal is generated by at least one first data path having a first worst propagation delay; the second data signal is generated by at least one second data path having a second worst propagation delay that is greater than the first worst propagation delay; and the second threshold is lower than the first threshold.
3 . The circuit of claim 1 , wherein: the first threshold is a status threshold at a first time distance from a clock edge of the clock signal of the circuit received by the first synchronous device following the arrival of the first data signal; and the second threshold is an alarm threshold at a second time distance from a clock edge of the clock signal of the circuit received by the second synchronous device following the arrival of the second data signal, the second threshold being lower than the first threshold.
4 . The circuit of claim 1 , comprising a plurality of said second timing guard circuits, and a protection circuit configured to: receive alarm flag signals from the plurality of second timing guard circuits when the slack time of the second data signal falls below the second threshold; and apply, in response to the alarm signal from any of the second timing guard circuits, a second frequency reduction to the clock signal of the circuit.
5 . The circuit of claim 4 , wherein the first frequency reduction is of up to 30 percent, and the second frequency reduction is of over 30 percent.
6 . The circuit of claim 5 , wherein the timing response circuit is configured to implement the second frequency reduction within 10 clock cycles, and preferably within 5 clock cycles, of the clock signal of the circuit from the assertion of the alarm flag signal.
7 . The circuit of claim 1 , wherein each of the first and second timing guard circuits comprises: a first delay buffer coupled between its clock input and a clock input node of the first synchronous device.
8 . The circuit of claim 1 , wherein each of the first and second timing guard circuits comprises: a second delay element and third delay element coupled in series between to its data input and a data input of a further synchronous device, wherein the delay introduced by the third delay element of each of the first timing guard circuit is different to the delay introduced by the third delay element of the second timing guard circuit.
9 . A method of timing control in a circuit, the method comprising: detecting, by each of a plurality of first timing guard circuits, when a slack time of a first data signal arriving at a first synchronous device falls below a first threshold; detecting, by a second timing guard circuit, when a slack time of a second data signal arriving at a second synchronous device falls below a second threshold, the first and second thresholds being different from each other; receiving, by the timing response circuit, status flag signals from the plurality of first timing guard circuits when the slack time of the first data signal falls below the first threshold; comparing, by the timing response circuit, a number of flag signals generated by the plurality of first timing guard circuits with a threshold; and applying, by the timing response circuit in response to the number of flag signals exceeding the threshold, a first supply voltage or biasing voltage adjustment and/or a first frequency reduction to a clock signal of the circuit.
10 . The method of claim 9 , wherein: the first data signal is generated by at least one first data path having a first worst propagation delay; the second data signal is generated by at least one second data path having a second worst propagation delay that is greater than the first worst propagation delay; and the second threshold is lower than the first threshold.
11 . The method of claim 9 , wherein: the first threshold is a status threshold at a first time distance from a clock edge of the clock signal of the circuit received by the first synchronous device following the arrival of the first data signal; and the second threshold is an alarm threshold at a second time distance from a clock edge of the clock signal of the circuit received by the second synchronous device following the arrival of the second data signal, the second threshold being lower than the first threshold.
12 . The method of claim 9 , wherein the circuit comprises a plurality of said second timing guard circuits and a protection circuit, the method further comprising: receiving, by the protection circuit, alarm flag signals from the plurality of second timing guard circuits when the slack time of the second data signal falls below the second threshold; and applying, by the protection circuit in response to the alarm signal from any of the second timing guard circuits, a second frequency reduction to the clock signal of the circuit.
13 . A circuit comprising: a first timing guard circuit configured to detect when a slack time of a first data signal arriving at a first synchronous device falls below a first threshold; a plurality of second timing guard circuits each configured to detect when a slack time of a second data signal arriving at a second synchronous device falls below a second threshold, the first and second thresholds being different from each other; and a protection circuit configured to: receive alarm flag signals from the plurality of second timing guard circuits when the slack time of the second data signal falls below the second threshold; and apply, in response to the alarm signal from any of the second timing guard circuits, a second frequency reduction to a clock signal of the circuit.

Description

The present patent application is a 35 U.S.C. § 371 national stage patent application of Patent Cooperation Treaty application number PCT/EP2022/069841, filed Jul. 15, 2022, titled “CIRCUIT FOR DETECTING TIMING VIOLATIONS IN A DIGITAL CIRCUIT,” which claims the benefit of and priority to French patent application filed on 15 Jul. 2021 and assigned application no. FR2107642, the entire contents of each of which applications is hereby incorporated herein by reference. TECHNICAL FIELD The present disclosure relates generally to the field of digital circuits, and in particular to the detection of potential timing violations in a digital circuit. BACKGROUND ART It has been proposed to improve circuit performance and/or reduce energy consumption by modifying clock frequencies and/or supply voltages supplied to areas of integrated circuits. However, beyond a certain operating point corresponding to a clock frequency and supply voltage limit, the circuit will no longer function correctly. In particular, an integrated circuit will no longer maintain correct functionality if one or more of its synchronous devices are subjected to timing violations. Synchronous devices include flip-flops, memories and latches. Such devices are generally characterized by a setup time tS that should be respected in order to ensure stability. The setup time tS defines a time period before a significant clock edge during which the input data of the synchronous device should not change. A timing violation occurs if the setup time is not respected. A static timing analysis of an integrated circuit design can identify one or more critical transmission paths, which are the transmission paths with the longest propagation delays between two synchronous devices in the circuit. The propagation delays on these critical transmission paths are generally used to determine the maximum permitted clock frequency of the circuit. However, using static timing analysis to determine the maximum permitted clock frequency at various operating voltages does not allow certain variables such as PVT-RC (process, voltage, temperature, resistance-capacitance parasitics) variations to be considered. Thus, it is necessary to allow relatively large margins, leading to inefficient operation. Monitoring circuits have been proposed that permit PVT-RC variations to be evaluated during circuit operation. Among such circuits, in-situ/in-field timing monitors have the advantage of being placed in the actual signal propagation paths in the circuit, and thus provide an accurate and localized indication of when timing violations may occur. However, there are technical difficulties in equipping a digital circuit with in-situ timing monitors in an effective manner, and in controlling the supply voltage and/or operating frequency of the circuit in an effective manner based on the outputs of the in-situ timing monitors. SUMMARY OF INVENTION According to one aspect, there is provided a circuit comprising: a first timing guard circuit configured to detect when a slack time of a first data signal arriving at a first synchronous device falls below a first threshold; anda second timing guard circuit configured to detect when a slack time of a second data signal arriving at a second synchronous device falls below a second threshold, the first and second thresholds being different from each other. According to one embodiment: the first data signal is generated by at least one first data path having a first worst propagation delay;the second data signal is generated by at least one second data path having a second worst propagation delay that is greater than the first worst propagation delay; andthe second threshold is lower than the first threshold. According to one embodiment: the first threshold is a status threshold at a first time distance from a clock edge of a clock signal of the circuit received by the first synchronous device following the arrival of the first data signal; andthe second threshold is an alarm threshold at a second time distance from a clock edge of the clock signal of the circuit received by the second synchronous device following the arrival of the second data signal, the second threshold being lower than the first threshold. According to one embodiment, the circuit comprises a plurality of said first timing guard circuits, and a timing response circuit, implemented for example by a status flag processing circuit and a control circuit, configured to: receive status flag signals from the plurality of first timing guard circuits when the slack time of the first data signal falls below the first threshold;compare a number of flag signals generated by the plurality of first timing guard circuits with a threshold; andapply, in response to the number of flag signals exceeding the threshold, a first supply voltage or biasing voltage adjustment and/or a first frequency reduction to the clock signal of the circuit. According to one embodiment, the circuit comprises a plural